tag: DRAM

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer 
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enh... » read more

DDR5 PMICs Enable Smarter, Power-Efficient Memory Modules
By Tim Messegee - 16 May, 2024 - Comments: 0

Power management has received increasing focus in microelectronic systems as the need for greater power density, efficiency and precision have grown apace. One of the important ongoing trends in service of these needs has been the move to localizing power delivery. To optimize system power, it’s best to deliver as high a voltage as possible to the endpoint where the power is consumed. Then a... » read more

SRAM Security Concerns Grow
By Karen Heyman - 09 May, 2024 - Comments: 0

SRAM security concerns are intensifying as a combination of new and existing techniques allow hackers to tap into data for longer periods of time after a device is powered down. This is particularly alarming as the leading edge of design shifts from planar SoCs to heterogeneous systems in package, such as those used in AI or edge processing, where chiplets frequently have their own memory hi... » read more

Centauri: Practical Rowhammer Fingerprinting Demonstrated On DRAM Modules (UC Davis)
By Technical Paper Link - 30 Apr, 2024 - Comments: 0

A technical paper titled “Centauri: Practical Rowhammer Fingerprinting” was published by researchers at UC Davis. Abstract: "Fingerprinters leverage the heterogeneity in hardware and software configurations to extract a device fingerprint. Fingerprinting countermeasures attempt to normalize these attributes such that they present a uniform fingerprint across different devices or present d... » read more

Exploring Process Scenarios To Improve DRAM Device Performance
By Yu De Chen - 18 Apr, 2024 - Comments: 0

In the world of advanced semiconductor fabrication, creating precise device profiles (edge shapes) is an important step in achieving targeted on-chip electrical performance. For example, saddle fin profiles in a DRAM memory device must be precisely fabricated during process development in order to avoid memory performance issues. Saddle fins were introduced in DRAM devices to increase channel l... » read more

Review Of Virtual Wafer Process Modeling And Metrology For Advanced Technology Development
By Coventor - 17 Apr, 2024 - Comments: 0

Semiconductor logic and memory technology development continues to push the limits of process complexity and cost, especially as the industry migrates to the 5 nm node and beyond. Optimization of the process flow and ultimately quantifying its physical and electrical properties are critical steps in yielding mature technology. The standard build, test, and wait model of technology development ... » read more

Memory On Logic: The Good And Bad
By Brian Bailey - 11 Apr, 2024 - Comments: 0

The chip industry is progressing rapidly toward 3D-ICs, but a simpler step has been shown to provide gains equivalent to a whole node advancement — extracting distributed memories and placing them on top of logic. Memory on logic significantly reduces the distance between logic and directly associated memory. This can increase performance by 22% and reduce power by 36%, according to one re... » read more

LPDDR5X Opening New Markets For Low-Power DRAMs
By Shyam Sharma - 11 Apr, 2024 - Comments: 0

Low-power DDR SDRAM has been one of the most widely used memories in the semiconductor market. This blog post talks about the evolutions of LPDDR DRAMs leading to the latest published standard of LPDDR5/5X. We also look at some of the traditional markets for LPDDR devices and how LPDDR5X is opening new specialized markets for the LPDDR DRAMs. History of LPDDR devices The first LPDDR standard,... » read more

Performance Boost In Powerful Real-Time Cortex-R Processor Using Data Prefetch Control
By Arm - 10 Apr, 2024 - Comments: 0

High-performance processors employ hardware data prefetching to reduce the negative performance impact of large main memory latencies. An effective prefetching mechanism can improve cache hit rate significantly. Data prefetching boosts the execution performance by fetching data before it is needed. While prefetching improves performance substantially on many programs, it can significantly red... » read more

Using Palladium To Address Contact Issues Of Buried Oxide Thin Film Transistors
By Technical Paper Link - 09 Apr, 2024 - Comments: 0

A new technical paper titled "Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway" was published by researchers at Tokyo Institute of Technology and National Institute for Materials Science (NIMS). Abstract "Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures... » read more

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