tag: DRAM

Executive Insight: Sehat Sutardja
By Ed Sperling - 11 Jan, 2016 - Comments: 1

Sehat Sutardja, chairman and CEO of Marvell, sat down with Semiconductor Engineering to talk about new approaches for design and memory and why costs and time to market are forcing changes in Moore's Law. What follows are excerpts of that conversation. SE: What was behind your move into modular packaging? Sutardja: The cost of building chips is getting out of hand. As we make things more ... » read more

Changes In Chip Design
By Ernest Worthman - 07 Jan, 2016 - Comments: 0

We all know that sub-10nm is coming. But is that really what will define the next generation of semiconductors? Progress in semiconductor technology increasingly is not just about advancements in the hardware. It also involves advancements in applications and technologies peripheral to the devices themselves. That may sound counterintuitive, but going forward the technology, applications and... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 24 Dec, 2015 - Comments: 0

South Korea’s SK Hynix led the initial charge in the development of High Bandwidth Memory (HBM), a 3D DRAM technology based on a memory stack and through-silicon vias (TSVs). SK Hynix has been shipping HBM parts in the market. Now, SK Hynix and Samsung are readying the next version of the technology, dubbed High Bandwidth Memory 2 or HMB2, according to a report from The Electronic Times of So... » read more

Rethinking Memory
By Ed Sperling - 16 Dec, 2015 - Comments: 3

Getting data in and out of memory is as important as the speed and efficiency of a processor, but for years design teams managed to skirt the issue because it was quicker, easier and less expensive to boost processor clock frequencies with a brute-force approach. That worked well enough prior to 90nm, and adding more cores at lower clock speeds filled the gap starting at 65nm. After that, th... » read more

Manufacturing Bits: Dec. 15
By Mark LaPedus - 15 Dec, 2015 - Comments: 0

DRAM scaling sans EUV At the recent IEEE International Electron Devices Meeting (IEDM) in Washington, D.C., chipmakers presented papers on several technologies, including one unlikely topic—DRAM scaling. For years, it was believed that DRAMs would hit the wall and stop scaling at 20nm or so. Then, at that point, the industry would need to migrate to a 3D DRAM structure or a next-generatio... » read more

Reflections On 2015
By Brian Bailey - 10 Dec, 2015 - Comments: 0

It is easy to make predictions, but few people can make them with any degree of accuracy. Most of the time, those predictions are forgotten by the end of the year and there is no one to do a tally of who holds more credibility for next year. Not so with Semiconductor Engineering. We like to hold people's feet to the fire, but while the "Pants-On-Fire" meter may be applicable to politicians, we ... » read more

Innovation Matters
By Zining Wu - 09 Dec, 2015 - Comments: 0

Innovation is not something that just happens. It requires a culture that rewards innovation, and the only way to make that happen is with buy-in at every level. What's needed is a climate for building, inventing and designing ICs and systems that push technology boundaries and help move the industry forward. This is a key ingredient for innovation that has been used across the globe to brin... » read more

On-Chip Networks Optimize Shared Memory For Multicore SoCs
By Sonics - 23 Nov, 2015 - Comments: 0

Performance of multicore SoCs is often dominated by external DRAM access, particularly in digital consumer devices running high quality video and graphics applications. Increasing core counts and newer DRAMs make the problems much more difficult. This article covers optimization of the on-chip network and memory system to achieve the required system throughput. For more information, click here. » read more

Overcoming The Design Bottleneck
By Brian Bailey - 12 Nov, 2015 - Comments: 0

SoCs control most advanced electronics these days and functionality, quality, power and security are a combination of both hardware and software. All throughout the development of today's complex systems, the memory hierarchy has remained the same—preserving the notion of a continuous computing paradigm. Today, that decision is leading to performance and power issues. There are several rea... » read more

High Speed Memory Interface Chipsets Let Server Performance Fly
By Rambus - 11 Nov, 2015 - Comments: 0

The demands on server performance continue to increase at a tremendous pace. New requirements from large in-memory databases that are powering today’s cloud services and advanced analytics tools are arriving just as the impact of Moore’s Law is starting to slow. This is setting up a classic performance challenge that requires rethinking some of the core elements of today’s server archit... » read more

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