tag: DRAM

Mixing Custom And Standard Parts
By Ed Sperling - 08 Aug, 2013 - Comments: 0

By Ed Sperling The amount of third-party and re-used IP content in an SoC is on the rise, but once a decision to buy vs. make has been made it doesn’t always stay that way. In fact, chipmakers are swinging the pendulum back and forth across a variety of chips, building IP themselves, standardizing on another vendor’s IP, then sometimes rolling it back the other way. The reasons are usua... » read more

The Week In Review: July 22
By Mark LaPedus - 22 Jul, 2013 - Comments: 0

By Mark LaPedus ASML Holding has been under pressure to bring extreme ultraviolet (EUV) lithography into mass production. EUV is still delayed. Now, in their latest roadmaps, leading-edge chipmakers are counting on ASML’s 300mm EUV scanner for insertion at the 10nm node. Yet, at the same time, ASML also is working on a 450mm version of the EUV tool. “EUV (on 300mm) is a higher priority th... » read more

Memory Gets Smarter
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Look inside any complex SoC these days and the wiring congestion around memory is almost astounding. While the number of features on a chip is increasing, they are all built around the same memory modules. Logic needs memory, and in a densely packed semiconductor, the wires that connect the myriad logic blocks are literally all over the memory. This is made worse by the fact ... » read more

Mobile Memory Madness
By Ed Sperling - 15 Nov, 2012 - Comments: 0

By Mark LaPedus The insatiable thirst for more bandwidth in smartphones, tablets and other devices has prompted an industry standards body to revamp its mobile memory interface roadmap. As part of the changes, the Joint Electron Devices Engineering Council (JEDEC) has scaled back the initial version of Wide I/O technology and pushed out the introduction date of a true 3D stacked architectur... » read more

Uneven Growth Ahead
By Joanne Itow - 18 Oct, 2012 - Comments: 0

By Joanne Itow SEMI recently released its silicon shipment forecast for 2012-2014. Total wafer shipments are expected to reach record levels in 2013 and 2014. Semico’s Wafer Demand model concurs with that forecast. Wafer demand is expected to grow at a compound annual rate of 11.7% over the next five years. The wafer demand pie keeps getting bigger but all the pieces are not growing at th... » read more

Thanks For The Memories
By Ed Sperling - 27 Sep, 2012 - Comments: 0

By Ed Sperling The amount of real estate in a design now devoted to memories—SRAM on chip, DRAM off chip, and a few other more exotic options showing up occasionally—is a testament to the amount of data that needs to be utilized quickly in both mobile and fixed devices. Memory is almost singlehandedly responsible for the routing congestion now plaguing complex SoCs. It is one of the mai... » read more

Universal Memories Fall Back To Earth
By Ed Sperling - 20 Sep, 2012 - Comments: 0

By Mark LaPedus Ten years ago, Intel Corp. declared that flash memory would stop scaling at 65nm, prompting the need for a new replacement technology. Thinking the end was near for flash, a number of companies began to develop various next-generation memory types, such as 3D chips, FeRAM, MRAM, phase-change memory (PCM), and ReRAM. Many of these technologies were originally billed as “uni... » read more

The End of the DRAM Era – Flash Spending Surpasses DRAM
By SEMI - 06 Oct, 2011 - Comments: 0

By Clark Tseng, SEMI Industry Research and Statistics, Taiwan The semiconductor memory industry has a long history of fluctuating market cycles. The DRAM sector in particular has gone through a few bad cycles and witnessed quite a few consolidations in the past ten years or so.  However, DRAM continues to be one of the most important and capital intensive sectors in the semiconductor indust... » read more

What’s Next After DRAM?
By Ed Sperling - 26 Aug, 2010 - Comments: 0

By Pallab Chatterjee At the most recent Denali Memcon, there was a panel discussion and debate about the future of DRAM and possible successor technologies. The discussion was moderated by Cadence’s Steve Leibson and featured Bob Merritt of Convergent Semiconductor, Barry Hoberman of Crocus, Ed Doller of Micron and Marc Greenberg of Denali/Cadence. The topic of the discuss was based on t... » read more

Soft Errors Create Tough Problems
By Ed Sperling - 28 Apr, 2009 - Comments: 0

By Ed Sperling Single event upsets used to be as rare as some elements on the Periodic Table, with the damage they could cause relegated more to theory than reality. Not anymore. At 90nm, what was theory became reality. And at 45nm, the events are becoming far more common, often affecting multiple bits in increasingly dense arrays of memory and now, increasingly, in the logic. Known alter... » read more

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