Manufacturing Bits: July 1

Nanotubes in 4D; Intel’s all-spin logic; Samsung’s 3D DRAMs.


Nanotubes in 4D
The California Institute of Technology (Caltech) has continued to advance its efforts in four-dimensional electron microscopy.

In 4D microscopy, electrons bombard a sample. Each electron scatters off the sample. This produces an image at just a femtosecond in duration. Then, millions of the images are stitched together, which, in turn, produces a digital movie in 4D.

Caltech researchers used 4D electron microscopy to visualize and monitor the flow of molten lead within single zinc oxide nanotubes in real time and space. (Source: Caltech)

Caltech researchers used 4D electron microscopy to visualize and monitor the flow of molten lead within single zinc oxide nanotubes in real time and space. (Source: Caltech)

Using the technology, researchers from Caltech observed the fluid dynamics in a single zinc oxide nanotube with the high spatial and temporal resolution. They also visualized and monitored the flow of molten lead within a nanotube in real time and space.

In the lab, the nanotube was filled with metallic lead. Then, a short electron pulse created an image of the hot liquid. The temporal changes of the images enabled researchers to study the viscous friction within the nanotube.

Researchers also captured how the hot pressurized liquid moved within the tubes. “These observations are particularly significant because visualizing the behavior of fluids at the nanoscale is essential to our understanding of how materials and biological channels effectively transport liquids,” said Ahmed Zewail, the Linus Pauling Professor of Chemistry at Caltech, on the university’s Web site.

Intel’s all-spin logic
All-spin logic has been proposed as a potential candidate for the post-CMOS era, which could occur at the 3nm node and beyond.

Intel and the Georgia Institute of Technology have devised an all-spin logic device and the associated interconnects for the technology. In all-spin logic, “binary information is stored in the magnetization of magnets that communicate using spin currents,” according to a recent paper from Intel and Georgia Tech. “These pure spin currents can be detected at the receiver magnet through the spin-torque effect.”

The interconnect element in a metallic all-spin logic device is what researchers call the non-local spin valve (NLSV). In the NLSV, current flows from the power supply to ground via input ferromagnet (FM) as well as the nonmagnetic metal underneath it. The current becomes spin polarized with the majority electrons’ magnetic moment aligned with its magnetization.

“The spin polarized electrons injected (or extracted) by the input magnet increase (or decrease) the density of the electrons with the spin orientation aligned with the input FM inside the interconnect. The concentration gradients for electrons with parallel and anti-parallel spin orientations inside the interconnect creates a spin current towards the output magnet based on the diffusion process. This spin current applies a torque to the output magnet that, if strong enough, can flip it to align with the spin orientation of the majority electrons,” according to researchers.

There are issues with interconnects in all-spin logic, however. “This is due to the exponential drop in spin signal as spin relaxation length degrades due to size effects,” according to researchers.

To solve the problem, there are several materials that can be used for the channel. There are metals (copper and aluminum), semiconductors (silicon and GaAs) and even graphene. Metals, according to researchers, have an advantage due to their high conductivity. This helps to reduce the conductivity mismatch problem prevalent in spin devices.

Two interconnect lengths of 80nm and 400nm were considered. “Aluminum wires offer a larger spin relaxation length and less pronounced size effects as compared to copper wires,” according to the paper. “However, they are more resistive except for narrow wires. Thereby, aluminum all-spin logic interconnects outperform copper all-spin logic interconnects when are they are relatively long and narrow.”

Samsung’s 3D DRAMs
3D DRAMs are generating steam. Micron has recently rolled out a 3D DRAM technology called the Hybrid Memory Cube (HMC). And SK Hynix is separately developing a 3D DRAM scheme called high bandwidth memory (HBM).

Samsung and Georgia Tech recently presented a research paper on 3D DRAMs, based on two technologies. One is a 4-tier cell/logic-mixed partitioning technology. The other is a 5-tier cell/logic-split style, which resembles the die partitioning used in the HMC.

In the cell/logic-mixed partitioning style, there are four dies stacked on top of each other. They are identical except for the bottom die, which is a master die. The stack is connected using through-silicon vias (TSVs).

Each die contains DRAM cells and a small amount of logic. More specifically, each die contains 8-Gb of DRAM cells, 400 signal TSVs, and 100 power/ground (P/G) TSVs. The TSVs are based on a via-last technology with a 10um diameter and 60um pitch. The designs are based on a 20nm PDK. The data rate of the 3D stacked DDR3SDRAM is 1,600-Mbps based on the burst length of 8.

There were some issues with this design, however. “First, the large area of I/O pads and buffers is expected to become more serious with today’s 20-30nm DRAM process technology since their size may not scale as DRAM cell technology,” according to researchers. “Second, the package bumps below I/O pads cause nontrivial reliability problems in DRAM cells. This is mainly caused by the coefficient of thermal expansion (CTE) mismatch among various materials in that area. This leads to a highly compressive stress on dies which contain DRAM cells.”

Researchers also devised a different 3D DRAM design based on a cell/logic-split technology. This design incorporates 5 tiers of DRAM dies. It provides 32-Gb of DDR3 memory. Each die contains 656 signal TSVs in the middle, and 100 P/G TSVs on both the top and bottom. The bottom master die contains peripheral components, I/O pads, buffers, and serializer/deserializers.

Each technology has its pluses and minuses. “The cell/logic split partitioning style outperforms or shows comparable results to the cell/logic-mixed style in area, reliability, power, and performance,” according to the paper. “On the other hand, the cell/logic-mixed style shows less TSV count and lower bonding costs.”

In the cell/logic split partitioning style, researchers used a more advanced process technology in the master die, which reduced the size of logic devices by up to 27%. It operated at a Vdd at 1.3 Volt. This saving leads to the total power consumption reduction of 23.6% for write operation and 27.3% for read operation in the split design at 1.3 Volt Vdd, according to researchers.