tag: DRAM

A Practical DRAM-Based Multi-Level PIM Architecture For Data Analytics
By Technical Paper Link - 20 Jul, 2023 - Comments: 0

A technical paper titled "Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics" was published by researchers at Korea Advanced Institute of Science & Technology (KAIST) and SK hynix Inc. Abstract: "Processing-in-memory (PIM) architecture is an inherent match for data analytics application, but we observe major challenges to address when accelerating it usi... » read more

RowPress: Read-Disturb Phenomenon In DDR4 DRAM Chips
By Technical Paper Link - 15 Jul, 2023 - Comments: 0

A technical paper titled "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" was published by researchers at ETH Zürich. Abstract: "Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and clo... » read more

Week In Review: Semiconductor Manufacturing, Test
By Gregory Haley - 07 Jul, 2023 - Comments: 0

China retaliated against a U.S. embargo on advanced semiconductor equipment exports by restricting exports of gallium and germanium. Both metals are widely used in semiconductors and electric vehicles. Despite export controls for advanced chips and equipment imposed on Chinese foundries by the U.S. and its allies, TrendForce predicts China's 300mm market share likely will increase from 24% ... » read more

DRAM Translation Layer, Mechanism for Flexible Address Mapping and Data Migration Within CXL-Based Memory Devices
By Technical Paper Link - 06 Jul, 2023 - Comments: 0

A technical paper titled “DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory” was published by researchers at Seoul National University. Abstract: "Memory disaggregation is a promising solution to scale memory capacity and bandwidth shared by multiple server nodes in a flexible and cost-effective manner. DRAM power consumption, which is reported to be... » read more

Low Density Of LPDDR4x DRAM — The Best Choice For Edge AI
By Winbond - 05 Jul, 2023 - Comments: 0

Edge AI computes the data as close as possible to the physical system. The advantage is that the processing of data does not require a connected network. The computation of data happens near the edge of a network, where the data is being developed, instead of in a centralized data-processing center. One of the biggest benefits of edge AI is the ability to secure real-time results for time-sensi... » read more

Improving DRAM Device Performance Through Saddle Fin Process Optimization
By Taeyon (TY) Oh - 15 Jun, 2023 - Comments: 0

As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced to increase channel length, prevent short channel effects, and increase data retention times [1]. However, at technology nodes beyond 20nm, securing sufficient device performance (su... » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Uncovering The Size, Structure, And Operation Of DRAM Subarrays And Showing Experimental Results Supporting The Cause Of Rowhammer
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for accurate information about the internal structure and characteristics of dynamic random-access memory (DRAM) has been on the rise. Recen... » read more

A PIM Architecture That Supports Floating Point-Precision Computations Within The Memory Chip
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications” was published by researchers at Rochester Institute of Technology and George Mason University. Abstract: "Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learnin... » read more

Rowhammer Vulnerability Of A HBM2 DRAM Chip
By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A new technical paper titled "An Experimental Analysis of RowHammer in HBM2 DRAM Chips" was published by researchers at ETH Zurich and American University of Beirut. Abstract: "RowHammer (RH) is a significant and worsening security, safety, and reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it is important to understand real DRAM chips' ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy