Optimize Physical Verification Cost Of Ownership

By Manoz Palaparthi - 29 Jul, 2021 - Comments: 0

As semiconductor designs continue to grow in size and complexity, they put increasing pressure on every stage of the design process. Physical verification, often on the critical path to tape-out, is especially affected. Design rule checking (DRC), layout versus schematic (LVS), and other physical verification runs take longer as chip size increases. In addition, finer geometries introduce new c... » read more

Tape Out On Time With Demand Signoff DRC In P&R

By Siemens EDA - 28 Jul, 2021 - Comments: 0

Physical characteristics of devices have become progressively more complex even as design companies pack more devices on each die. Combining these characteristics with ever more demanding chip power, performance, and area (PPA) goals not only result in increased resource utilization but also challenge existing tools/flows/techniques. Adding on-demand signoff-quality DRC verification inside P&R ... » read more

Signoff DRC In P&R Lets You Get Better Products To Market Faster

By Srinivas Velivala - 27 May, 2021 - Comments: 0

Trust is generally a reflection of quality. You trust someone, be it an individual or a company, because they have, over time, consistently performed high-quality work. You trust a product because your past experience with that product has been positive, or the experiences of lots of other people have been positive. With that said, quality comes in shades and percentages. Most of us will happil... » read more

MaxLinear And Calibre RealTime Digital

By Siemens EDA - 26 May, 2021 - Comments: 0

MaxLinear implemented the Calibre RealTime Digital interface for fast, iterative, signoff DRC checking and fixing during floorplanning and placement. They not only reduce the total of batch DRC iterations, but also eliminate potential late-stage issues during final physical verification signoff that are exponentially harder to fix. Adopting the Calibre RealTime Digital interface enabled MaxLine... » read more

Re-Architecting SerDes

By Brian Bailey - 10 Dec, 2020 - Comments: 0

Serializer/Deserializer (SerDes) circuits have been helping semiconductors move data around for years, but new process technologies are forcing it to adapt and change in unexpected ways. Traditionally implemented as an analog circuit, SerDes technology has been difficult to scale, while low voltages, variation, and noise are making it more difficult to yield sufficiently. So to remain releva... » read more

Choosing Between Static and Dynamic Shapes

By Tyler Lockman - 14 May, 2020 - Comments: 0

That title might be a touch misleading. We’re not here to talk about why to convert shapes between static and dynamic. Rather, I want to talk about why you should NOT be doing this. Every design has some conductor shapes in it (or at least a very large percentage of them). What style to use is a choice that will impact performance through your entire flow; let the shape’s purpose guide you.... » read more

Reducing IR And EM Issues With Automated Via Insertion

By Mentor, a Siemens Business - 25 Mar, 2020 - Comments: 0

IR drop and EM issues are significant performance and reliability detractors at advanced nodes. Adding vias is the most effective means of correction, but traditional custom scripts are difficult and time-consuming, and do not guarantee correct-by-construction vias. The Calibre YieldEnhancer PowerVia utility uses manufacturing requirements to perform automated insertion of DRC/LVS-clean vias. R... » read more

Balancing Flexibility And Quality In SRAM Verification

By Elven Huang - 30 Jan, 2020 - Comments: 0

Memory is an essential component of system-on-chip (SOC) designs, especially at advanced nodes. SoCs use a variety of memory block types, such as static random-access memory (SRAM) and dynamic RAM (DRAM), to perform computations. The SRAM blocks, which consist of an assembly of specialized calls that abut or overlap one another in a specific arrangement that complies with the circuit specificat... » read more

Speeding Up Process Optimization Using Virtual Fabrication

By Coventor - 22 Jan, 2020 - Comments: 0

Author: Joseph Ervin Director, Semiconductor Process and Integration Lam Research Advanced CMOS scaling and new memory technologies have introduced increasingly complex structures into the device manufacturing process. For example, the increase in NAND memory layers has achieved greater vertical NAND scaling and higher memory density, but has led to challenges in high aspect ratio etch patte... » read more

Enhancing IO Ring Checks For Consistent, Customizable Verification

By Mentor, a Siemens Business - 25 Nov, 2019 - Comments: 0

The Calibre PERC IO ring checker framework eliminates manual checking by providing a robust DRC-like environment to verify all IO placement rules with sign-off quality. Running on the first LEF/DEF floorplan, the IO ring checker provides early and full coverage of IO ring placement rules, enabling changes with minimal impact on the layout. Fast, accurate debugging and correction ensures that So... » read more

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Knowledge Centers
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