tag: DVFS

Power Challenges At 10nm And Below
By Ann Mutschler - 11 May, 2017 - Comments: 1

Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Closing The Loop On Power Optimization
By Brian Bailey - 11 May, 2017 - Comments: 2

[getkc id="108" kc_name="Power"] has become a significant limiter for the capabilities of a chip at finer geometries, and making sure that performance is maximized for a given amount of power is becoming a critical design issue. But that is easier said than done, and the tools and methodologies to overcome the limitations of power are still in the early definition stages. The problem spans a... » read more

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Energy Harvesting Gains Steam
By Ann Mutschler - 10 Nov, 2016 - Comments: 0

Energy harvesting is gaining traction with a surge in ultra-low-power IoT applications, ranging from inventory tracking, wearables and drones, to vibration sensors for motors in industrial settings. The idea that machines could run without batteries—or that energy could be harvested either from motion or ambient sound waves or chemical reactions to augment battery power—has been in the w... » read more

Power Limits Of EDA
By Brian Bailey - 13 Oct, 2016 - Comments: 3

Power has become a major gating factor in semiconductor design. It is now the third factor in design optimization, along with performance, and is almost becoming more important than area. But there are limits to the amount of help that [getkc id="7" kc_name="EDA"] can provide with [getkc id="106" kc_name="power optimization"]. Power is not just an optimization problem. It is a design problem... » read more

Implementation Limits Power Optimization
By Ann Mutschler - 14 Jul, 2016 - Comments: 3

Implementation is still the step that makes or breaks power budgets in chip design, despite improvements in power estimation, power simulations, and an increase in the number of power-related architectural decisions. The reason: All of those decisions must be carried throughout the design flow. “If implementation decides to give up, then it doesn't really matter at the end of the day,” s... » read more

Power Management Heats Up
By Brian Bailey - 14 Apr, 2016 - Comments: 0

Power management has been talked about a lot recently, especially when it comes to mobile devices. But power is only a part of the issue—and perhaps not even the most important part. Heat is the ultimate limiter. If you cannot comfortably place the device on your face or wrist, then you will not have a successful product. Controlling heat, at the micro and macro levels, is an important asp... » read more

Powerful New Standard
By Brian Bailey - 02 Mar, 2016 - Comments: 1

In December 2015, the IEEE released the latest version of the 1801 specification, titled the IEEE standard for design and verification of low-power integrated circuits, but most people know it as UPF or the Unified Power Format. The standard provides a way to specify the power intent associated with a design. With it, a designer can define the various power states of the design and the contexts... » read more

Talk Fast And Stop
By Pat Sheridan - 25 Feb, 2016 - Comments: 0

Power management. If you’re responsible for the design of low-power, energy-efficient electronic systems and SoCs, you need to have a power management strategy and you need to know as soon as possible if it will meet the demands of your product and its target applications. For example, dynamic voltage and frequency scaling (DVFS) is a power management strategy that adjusts the frequency an... » read more

Three Steps To Complete Power-Aware Debug
By Ellie Burns - 28 Jan, 2016 - Comments: 0

In previous blogs, we’ve talked about UPF and the successive refinement low power flow developed by ARM and Mentor Graphics (you can find these here.) In this blog we’d like to walk through some typical debugging scenarios our customers face in their low power designs. So I’ve asked two of our low power debug experts, Gabriel Chidolue and Mark Handover, to join me to make sure you get ... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy