tag: dynamic power

Alchip Minimizes Dynamic Power For High-Performance Computing ASICs
By Mentor, a Siemens Business - 09 May, 2018 - Comments: 0

Alchip, a fabless ASIC provider, focuses on high-performance computing ASICs. They decided to undertake a new project where they would employ the PowerPro RTL Low-Power Platform to reduce dynamic power consumption within their unique fishbone clock tree methodology. Could they achieve better power results using PowerPro and could they integrate the tool within their team and the existing design... » read more

Lots Of Little Knobs For Power
By Ann Mutschler - 09 Nov, 2017 - Comments: 3

Dynamic power is becoming a much bigger worry at new nodes as more finFETs are packed on a die and wires shrink to the point where resistance and capacitance become first-order effects. Chipmakers began seeing dynamic power density issues with the first generation of [getkc id="185" kc_name="finFETs"]. While the 3D transistor structures reduced leakage current by providing better gate contro... » read more

Building Faster Chips
By Ed Sperling - 21 Jul, 2016 - Comments: 5

By Ed Sperling and Jeff Dorsch An explosion in IoT sensor data, the onset of deep learning and AI, and the commercial rollout of augmented and virtual reality are driving a renewed interest in performance as the key metric for semiconductor design. Throughout the past decade in which mobility/smartphone dominated chip design, power replaced performance as the top driver. Processors ha... » read more

Executive Insight: Grant Pierce
By Ed Sperling - 29 Jun, 2016 - Comments: 0

Grant Pierce, president and CEO of Sonics, sat down with Semiconductor Engineering to discuss new ways to increase energy efficiency in SoCs. What follows are excerpts of that conversation. SE: Looking out at the semiconductor industry there are a lot of changes underway right now. What are the biggest impacts from your perspective? Pierce: The amount of data that is being captured or sen... » read more

Near-Threshold Computing
By Brian Bailey - 16 Jun, 2016 - Comments: 2

The emergence of the Internet of Things (IoT) has brought a lot of attention to the need for extremely low-power design, and this in turn has increased the pressure for voltage reduction. In the past, each new process node shrunk the feature size and lowered the nominal operating voltage. This resulted in a drop in power consumption. However, the situation changed at about 90nm in two ways. ... » read more

An Introduction to Reducing Dynamic Power Using PowerPro
By Mentor, a Siemens Business - 14 Jun, 2016 - Comments: 0

At many companies, the job of power reduction is left to power experts. These experts have built up knowledge and methodologies over many years, which they repeatedly apply to designs in their groups. This approach is very narrow and it not scalable across multiple groups in the company. Companies have begun to realize the limitations of this approach. More and more RTL designers are being task... » read more

Plotting The Next Semiconductor Road Map
By Ed Sperling - 13 Jun, 2016 - Comments: 0

The semiconductor industry is retrenching around new technologies and markets as Moore's Law becomes harder to sustain and growth rates in smart phones continue to flatten. In the past, it was a sure bet that pushing to the next process node would provide improvements in power, performance and cost. But after 22nm, the economics change due to the need for multi-patterning and finFETs, and th... » read more

An Introduction To Reducing Dynamic Power
By Ellie Burns - 14 Apr, 2016 - Comments: 0

In the past few blogs we have been primarily talking about UPF and applying the Successive Refinement process to save power. But, this process addresses leakage power. In this session we want to talk about how to save dynamic power. As designs move to finFET technology, dynamic power is the dominant contributor to power consumption. Power consumption trend. I recently sat down with my c... » read more

2016 And Beyond
By Krishna Balachandran - 10 Dec, 2015 - Comments: 0

Greek mythology and Roman history are replete with soothsayers, some of whom got it right and others wrong. Cassandra was cursed that her predictions wouldn’t be believed, even though she predicted the Trojan horse. Caesar’s soothsayer predicted the demise of Julius Caesar during the Ides of March, which Caesar himself was skeptical about, but indeed he was murdered before the Ides passed. ... » read more

Tech Talk: 14nm And Stacked Die
By Ed Sperling - 11 Nov, 2015 - Comments: 0

Aashish Malhotra, marketing director for the ASIC Business Unit at GlobalFoundries, talks about 14nm process technology, the IP ecosystem, and why that technology node will be used as a platform for 2.5D and 3D stacked die across a wide range of markets including the Internet of Everything. [youtube vid=ukTRuedB7ZU] » read more

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