2016 And Beyond


Greek mythology and Roman history are replete with soothsayers, some of whom got it right and others wrong. Cassandra was cursed that her predictions wouldn’t be believed, even though she predicted the Trojan horse. Caesar’s soothsayer predicted the demise of Julius Caesar during the Ides of March, which Caesar himself was skeptical about, but indeed he was murdered before the Ides passed. ... » read more

Tech Talk: 14nm And Stacked Die


Aashish Malhotra, marketing director for the ASIC Business Unit at GlobalFoundries, talks about 14nm process technology, the IP ecosystem, and why that technology node will be used as a platform for 2.5D and 3D stacked die across a wide range of markets including the Internet of Everything. [youtube vid=ukTRuedB7ZU] » read more

Doing More With RTL Power Analysis: Smart Synthesis Architecture


Traditionally RTL power analysis has been used to understand the design power consumption so that package and power supply designs can start, and designers can then fix any power regression violations in subsequent design iterations. However, migration to finFET processes is causing designers to look at RTL power analysis differently at advanced nodes. FinFET processes have largely addressed... » read more

Moore’s Law Reset?


GlobalFoundries today took the wraps off its 22nm FD-SOI process, promising to extend Moore's Law technologically without altering the economic equation—at least for the next couple of process nodes. Subramani Kengeri, vice president of global design solutions at [getentity id="22819" comment="GlobalFoundries"], said 22nm FD-SOI will provide the same 30% improvement in PPA that has been c... » read more

Tech Talk: Power Tools


At 200 million gates, using standard tools for power will add weeks to the semiconductor design process. Vijay Chobisa, product marketing manager at Mentor Graphics, talks with Semiconductor Engineering about where the problems are and how to solve them. [youtube vid=w7yEdtaIb9A] » read more

Rethinking Power


Power typically has been the last factor to be considered in the PPA equation, and it usually was somebody else's problem. Increasingly it's everyone's problem, and EDA companies are beginning to look at power differently than in the past. While the driving forces vary by market and by process node, the need to save energy at every node and in almost all designs is pervasive. In the server m... » read more

Low Power Paradox


Power has been an important design challenge for quite some time. Leakage power started to grow in 90nm, and by 65nm it became a severe design issue. We have built many techniques to address leakage, most notably power gating. These techniques are complex and have an impact on the design as a whole. FinFET technologies are seen as a boon to this issue of leakage. There are references that qu... » read more

Experts At The Table: Low-Power Verification


By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss power format changes with Sushma Hoonavera-Prasad, design engineer in Broadcom’s mobile platform group; John Biggs, consultant engineer for R&D and co-founder of ARM; Erich Marschner, product marketing manager at Mentor Graphics; Qi Wang, technical marketing group director at Cadence; and Jeffrey Lee, corporate ap... » read more

Dealing With New Bottlenecks


By Ed Sperling While the number of options for improving efficiency and performance in designs continues to increase, the number of challenges in getting chips at advanced process nodes out the door is increasing, too. Thinner wires, routing congestion, more power domains, IP integration and lithography issues are conspiring to make design much more difficult than in the past. So why aren... » read more

Design Topology Requires Physical Data


By Ann Steffora Mutschler To best understand a design topology and make decisions on clock/register gating, vector sets are required for the RTL tools to understand how to gate clocks and registers. However, if certain constraints are set on all enabled signals in RTL they can be re-used for gating clocks and registers downstream where enablers are not available—even without needing a ... » read more

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