Changes In Auto Architectures

By Ed Sperling - 04 Aug, 2021 - Comments: 0

Automotive architectures are changing from a driver-centric model to one where technology supplements and in some cases replaces the driver. Hans Adlkofer, senior vice president and head of the Automotive Systems Group at Infineon, looks at the different levels of automation in a vehicle, what’s involved in the shift from domain to zonal architectures, why a mix of processors will be required... » read more

EDA, IP Numbers In Record Territory

By Ed Sperling - 16 Jul, 2021 - Comments: 0

EDA and semiconductor IP revenue soared to a new high, up 17% worldwide in Q1 compared to the same period in 2020, with revenue in China surging 73%, according to new data from SEMI's Electronic System Design Alliance. For many financial reports outside of semiconductors, strong growth numbers can be misleading because they reflect comparatively weak earnings stemming from pandemic-related s... » read more

Geopolitical And Economic Outlook For Chips And Equipment

By Ed Sperling - 17 Jun, 2021 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss geopolitical and economic changes and how they affect the chip industry with Jean-Christophe Eloy, CEO of Yole Developpement; Risto Puhakka, president of VLSI Research; Carolyn Evans, chief economist at Intel; Duncan Meldrum, chief economist at Hilltop Economics; and Rozalia Beica, head of the semiconductor business at AT&S... » read more

EDA In The Cloud

By Ann Mutschler - 09 Jun, 2021 - Comments: 0

Hagai Arbel, CEO of Vtool, talks with Semiconductor Engineering about the benefits of moving EDA tools to the cloud, why it has been slow to take off, and what will drive this trend in the future. » read more

Reliability Costs Becoming Harder To Track

By Ed Sperling And Susan Rambo - 08 Jun, 2021 - Comments: 0

Ensuring reliability in chips is becoming more complex and significantly more expensive, shifting left into the design cycle and right into the field. But those costs also are becoming more difficult to define and track, varying greatly from one design to the next based upon process node, package technology, market segment, and which fab or OSAT is used. As the number of options increases fo... » read more

Recalculating The Cost Of Test

By Ed Sperling - 11 May, 2021 - Comments: 0

The cost of test is rising. For decades, test was limited to a flat 2% of the cost of designing and manufacturing a chip. Today, no one is quite sure what that cost really is, and there doesn't seem to be any single formula for determining it. In some cases, there isn't even a sense of urgency to finding out. Several significant changes are occurring that make any formula difficult to cal... » read more

Shortages, Challenges Engulf Packaging Supply Chain

By Mark LaPedus - 18 Feb, 2021 - Comments: 0

A surge in demand for chips is impacting the IC packaging supply chain, causing shortages of select manufacturing capacity, various package types, key components, and equipment. Spot shortages in packaging surfaced in late 2020 and have since spread to other sectors. There are now a variety of choke points in the supply chain. Wirebond and flip-chip capacity will remain tight throughout 2021... » read more

Using Analytics To Reduce Burn-in

By Anne Meixner - 12 Jan, 2021 - Comments: 3

Silicon providers are using adaptive test flows to reduce burn-in costs, one of the many approaches aimed at stemming cost increases at advanced nodes and in advanced packages. No one likes it when their cell phone fails within the first month of ownership. But the problems are much more pressing when the key components in data warehouse servers or automobiles fail. Reliability expectations ... » read more

EDA, IP Revenue Up 15%

By Ed Sperling - 11 Jan, 2021 - Comments: 2

EDA and IP revenues blasted off in Q3 of 2020 in every geography and every sector, despite a trade war, a pandemic, and slowdowns in the automotive and avionics sectors. Revenue grew to $2.95 billion, up 15% over the $2.57 billion in the same period in 2019, according to a just-released report from the Electronic System Design Alliance Market Statistic Services (MSS). The four-quarter moving... » read more

CEO Outlook: 2021

By Ed Sperling - 04 Jan, 2021 - Comments: 0

The new year will be one of significant transition and innovation for the chip industry, but there are so many new applications and market segments that broad generalizations are becoming less meaningful. Unlike in years past, where sales of computers or smart phones were a good indication of how the chip industry would fare, end markets have both multiplied and splintered, greatly increasin... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

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Partitioning In The Chiplet Era

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by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?