Balancing Programmability And Performance In Cars

By Ann Mutschler - 05 Sep, 2024 - Comments: 0

The rate of change in the automotive industry is accelerating with the shift toward software-defined vehicles and ongoing advancements in algorithms and chip architectures. The challenge now is to figure out the best way to prevent rapid obsolescence, improve safety, and keep the cost of these changes to a minimum. Today, updatable automotive hardware is typically achieved through FPGAs, but... » read more

Adapting To Evolving IC Requirements

By Ed Sperling - 07 May, 2024 - Comments: 0

As chip designs become increasingly heterogeneous and domain-specific, packing a device with one-size-fits-all chips or chiplets doesn't make sense. The key is rightsizing different components based on real workloads, so they don't waste power when there is too little utilization of logic, and so they don't struggle to complete tasks because they are undersized. Jayson Bethurem, vice president ... » read more

Rethinking Chip Economics

By Ed Sperling - 20 Mar, 2024 - Comments: 0

As process nodes shrink, so does the selection of chips developed at those nodes. Consumers demand more features and functionality, but that carries a high price tag in terms of both complexity and real dollars. In addition, because costs are skyrocketing, there is growing pressure for those chips to remain reliable and up-to-date for longer periods of time. Jayson Bethurem, vice president of m... » read more

How Secure Are FPGAs?

By Karen Heyman - 04 Jan, 2024 - Comments: 1

The unique hybrid software/hardware nature of FPGAs makes them tempting targets for cyberattacks, while also enabling them to rebuff attacks and change the attack surface before significant damage can be done. But it's becoming increasingly challenging to address all the potential vulnerabilities. FPGAs are often included in larger systems, each with their own unique attack vectors as well a... » read more

Holistic Power Reduction

By Brian Bailey - 11 May, 2023 - Comments: 0

The power consumption of a device is influenced by every stage of the design, development, and implementation process, but identifying opportunities to save power no longer can be just about making hardware more efficient. Tools and methodologies are in place for most of the power-saving opportunities, from RTL down through implementation, and portions of the semiconductor industry already a... » read more

Performance Benchmarking Embedded FPGAs

By Flex Logix - 03 May, 2023 - Comments: 0

This Application Note has the following objectives: Provide performance benchmark achievable on the various EFLX IP Cores currently available; Provide performance variation for different process nodes; Provide performance benchmarks to compare with other embedded FPGAs. Click here to read more. » read more

Improving PPA When Embedding FPGAs Into SoCs

By Ed Sperling - 31 Jan, 2023 - Comments: 0

Embedded FPGAs have been on everyone’s radar for years as a way of extending the life of chips developed at advanced nodes, but they typically have come with high performance and power overhead. That’s no longer the case, and the ability to control complex chips and keep them current with changes to algorithms and various protocols is significant step. Geoff Tate, CEO of Flex Logix, talks a... » read more

Solving The Quantum Threat With Post-Quantum Cryptography On eFPGAs

By Flex Logix - 30 Nov, 2022 - Comments: 0

The quantum threat and post-quantum cryptography Advances in quantum computing technology threaten the security of current cryptosystems. Asymmetric cryptography algorithms that are used by modern security protocols for key exchange and digital signatures rely on the complexity of certain mathematical problems. Currently, the main problems used for asymmetric cryptography are integer f... » read more

Complex Tradeoffs In Inferencing Chips

By John Koon - 17 Oct, 2022 - Comments: 0

Designing AI/ML inferencing chips is emerging as a huge challenge due to the variety of applications and the highly specific power and performance needs for each of them. Put simply, one size does not fit all, and not all applications can afford a custom design. For example, in retail store tracking, it's acceptable to have a 5% or 10% margin of error for customers passing by a certain aisle... » read more

Put A Data Center In Your Phone!

By Andy Jaros - 10 Oct, 2022 - Comments: 0

Datacenters heavily leverage FPGAs for AI acceleration. Why not do the same for low power edge applications with embedded FPGA (eFPGA)? It’s common knowledge for anyone connected to the cloud computing industry that data centers heavily rely on FPGAs for programmable accelerators enabling high performance computing for AI training and inferencing. These heterogeneous computing solution... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?