tag: electromigration

The Brave New World Of FinFETs
By Ed Sperling - 10 Oct, 2013 - Comments: 0

SoCs using 16nm and 14nm finFETs are expected to begin rolling out next year using a 20nm back-end-of-line process. While the initial performance and power numbers are looking very promising, the challenges of designing and building these complex chips are daunting—and there are more problems on the way. First, the good news. Initial results from foundries show a 150% improvement in perfor... » read more

Aging: Not Always A Bad Thing
By Ann Mutschler - 22 Aug, 2013 - Comments: 0

By Ann Steffora Mutschler When IC devices are produced and shipped to end customers, it is important that they will function as specified in the application environment. Determining how a device will operate over time is a key aspect of overall reliability and is commonly referred to as ‘aging.’ Aging of electronics is not a new problem. In fact, analog and automotive designers have bee... » read more

EM Analysis At Advanced Nodes
By Valeriy Sukharev - 26 Jul, 2013 - Comments: 0

Going forward, a very different method of EM assessment can be proposed if we look at interconnect reliability from the position of its functionality, when the failure of the interconnect means its inability to function properly. The two most important functions of the chip interconnect are: Providing connectivity between different parts of design for proper signal propagations (signal circ... » read more

Experts At The Table: Who Pays For Low Power?
By Ed Sperling - 19 Jul, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss the cost of low power with Fadi Gebara, research staff member for IBM’s Austin Research Lab; David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Aveek Sarkar, vice president of product engineering and support at Apache Design; and Tim Whitfield, director o... » read more

EM Analysis At Advanced Nodes
By Valeriy Sukharev - 19 Jul, 2013 - Comments: 0

EM statistics Almost 50 years ago, James Black demonstrated experimentally that TTF of the metal line stressed by direct current (DC) of density j at the temperature T follows the dependency where k is the Boltzmann constant, and A is the proportionality coefficient, which can depend on line geometry, residual stress, and temperature. Two critical parameters, the current density exponen... » read more

Electromigration Analysis At Advanced Nodes
By Valeriy Sukharev - 11 Jul, 2013 - Comments: 0

Introduction Continuous downward scaling is challenging electromigration (EM) signoff using traditional EM checking approaches. The size reduction of metal line cross sections results in higher current densities, which are governed by technology scaling. With the transition to advanced technological nodes, the widely-predicted decrease in EM lifetime is responsible for the pessimistic performa... » read more

New Reliability Issues Emerge
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ed Sperling Most consumers define reliability by whether a device turns on and works as planned, but the term is becoming harder to define as complexity increases and systems are interconnected. Adding more functionality in less space has made it more difficult to build complex chips, and it has made it more difficult to prevent problems in those chips. Verification coverage is a persist... » read more

Experts At The Table: The Growing Signoff Headache
By Ed Sperling - 07 Jun, 2013 - Comments: 0

By Ed Sperling Low-Power/High-Performance Engineering sat down to discuss signoff issues with Rob Aitken, an ARM fellow; Sumbal Rafiq, director of engineering at Applied Micro; Ruben Molina, product marketing director for timing signoff at Cadence; Carey Robertson, director of product marketing for Calibre extraction at Mentor Graphics; and Robert Hoogenstryd, director of marketing for design ... » read more

Bringing Electrical Info To Design’s Forefront
By Ann Mutschler - 09 May, 2013 - Comments: 0

By Ann Steffora Mutschler To reflect the impact on transistors of smaller process nodes and the electrical effects that occur as a result, a shift is underway where the electrical analysis and verification that used to be done when the layout was complete is moving earlier in the design process. The analysis includes parasitic extraction of interconnect and device parasitics, electromigrati... » read more

Executive Briefing: Andrew Yang
By Ed Sperling - 09 May, 2013 - Comments: 0

By Ed Sperling Andrew Yang, president of ANSYS subsidiary Apache Design, sat down with Low-Power/High-Performance Engineering to talk about why power is becoming so important and where the future challenges lie. What follows are excerpts of that conversation. LPHP: What’s the most important issue these days for chipmakers? Yang: According to the feedback we’ve gotten from our customer... » read more

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