The Increasingly Ordinary Task Of Verifying RISC-V

By Ann Mutschler - 03 Jun, 2020 - Comments: 0

As RISC-V processor development matures and its usage in SoCs and microcontrollers grows, engineering teams are starting to look beyond the challenges of the processor core itself. So far, the majority of industry verification efforts have focused on ISA compliance to standardize the RISC-V core. Now the focus is shifting to be how to handle verification as the system grows, especially as this... » read more

(Artificially) Intelligent Verification

By Brian Bailey - 01 Jun, 2020 - Comments: 1

Functional verification produces a lot of data, , but does that make it suitable for Artificial Intelligence (AI) or Machine Learning (ML)? Experts weigh in about where and how AI can help and what the industry could do to improve the benefits. "It's not necessarily the quantity," says Harry Foster, chief scientist for verification at Mentor, a Siemens Business. "It's the quality that matter... » read more

A Different View On Debugging

By Hagai Arbel - 01 Jun, 2020 - Comments: 0

The classic approach to improve an engineering task that is becoming too complex due to its size and detail is to raise the abstraction of design representation. In this way we plan cities, build aircraft and plan 500M gate SoCs. For example, there is no way an ASIC design could go beyond a few thousand logic gates without shifting abstraction to the Register Transfer Level (RTL) and leveragin... » read more

Connecting Emulated Designs To Real PCIe Devices

By Krzysztof Szczur - 28 May, 2020 - Comments: 0

These days verification teams no longer question whether hardware assisted verification should be used in their projects. Rather, they ask at which stage they should start using it. Contemporary System-on-Chip (SoC) designs are already sufficiently complex to make HDL simulation a bottleneck during verification, without even mentioning hardware-software co-verification or firmware and softwa... » read more

What Will The Next-Gen Verification Flow Look Like?

By Ed Sperling - 28 May, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; and Nasr Ullah, senior director of performance architecture at SiFive. What follows are exc... » read more

Practical Processor Verification

By Brian Bailey - 23 Apr, 2020 - Comments: 0

Custom processors are making a resurgence, spurred on by the early success of the RISC-V ISA and the ecosystem that is rapidly building around it. But this shift is amid questions about whether processor verification has become a lost art. Years ago custom processors were common. But as the market consolidated around a handful of companies, so did the tools and expertise needed to develop th... » read more

Power Management Becomes Top Issue Everywhere

By Ann Mutschler - 12 Mar, 2020 - Comments: 1

Power management is becoming a bigger challenge across a wide variety of applications, from consumer products such as televisions and set-top-boxes to large data centers, where the cost of cooling server racks to offset the impact of thermal dissipation can be enormous. Several years ago, low-power design was largely relegated to mobile devices that were dependent on a battery. Since then, i... » read more

2019 – The Year Of The “Dynamic Duo” Of Emulation and Prototyping

By Frank Schirrmeister - 30 Jan, 2020 - Comments: 0

In technology, we are always trying to figure out when we have reached critical mass, have crossed the chasm, or even can be considered mainstream. We all have seen the adoption curves for consumer products. In design and verification technology, a distinct B2B setting with fewer end customers than in the B2C domain, the situation seems to be even worse as there is no “one flow” to design a... » read more

Big Design, IP and End Market Shifts In 2020

By Brian Bailey - 30 Jan, 2020 - Comments: 0

EDA is on a roll. Design starts are up significantly thanks to increased investment in areas such as AI, a plethora of new communications standards, buildout of the Cloud, the race toward autonomous driving and continued advancements in mobile phones. Many designs demand the latest technologies and push the limits of complexity. Low power is becoming more than just reducing wasted power at t... » read more

Achieving Functional Safety For Autonomous Vehicle SoC Designs

By Mentor, a Siemens Business - 03 Dec, 2019 - Comments: 0

Autonomous vehicle systems will be expected to meet rigorous safety standards regarding many aspects of system design and performance. One set of these standards, known as functional safety, focuses on the safety and reliability of the electrical and electronic systems within the vehicle, and the system-on-chip (SoC) devices in particular. As the complexity of these devices grows, autonomous ve... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: emulation