tag: EPFL

Chip Industry Week In Review
By The SE Staff - 15 Dec, 2023 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Synopsys acquired Imperas, pushing further into the RISC-V world with Imperas' virtual platform technology for verifying and emulating processors. Synopsys has been building up its RISC-V portfolio, starting with ARC-V processor IP and a full suite of tools introduced last month. The first high-NA EUV R&D center in the U.S. will be built at... » read more

Chip Industry Week In Review
By The SE Staff - 08 Dec, 2023 - Comments: 0

By Jesse Allen, Karen Heyman, and Liz Allan AMD took the covers off new AI accelerators for training and inferencing of large language model and high-performance computing workloads. In its announcement, AMD focused heavily on performance leadership in the commercial AI processor space through a combination of architectural changes, better software efficiency, along with some improvements in... » read more

Chip Industry Week In Review
By The SE Staff - 01 Dec, 2023 - Comments: 0

By Susan Rambo, Gregory Haley, and Liz Allan Amkor plans to invest about $2 billion in a new advanced packaging and test facility in Peoria, Arizona. When finished, it will employ about 2,000 people and will be the largest outsourced advanced packaging facility in the U.S. The first phase of the construction is expected to be completed and operational within two to three years. Synopsys p... » read more

Research Bits: November 21
By Jesse Allen - 21 Nov, 2023 - Comments: 0

MoS2 in-memory processor Researchers from École Polytechnique Fédérale de Lausanne (EPFL) developed a large-scale in-memory processor using the 2D semiconductor material, molybdenum disulfide (MoS2), for the channel material in the more than 1,000 transistors that comprise the processor. The MoS2-based in-memory processor is dedicated to vector-matrix multiplication, key for digital signal ... » read more

Chip Industry’s Technical Paper Roundup: October 17
By Liz Allan - 17 Oct, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=155 /] More Reading Technical Paper Library home » read more

Chip Industry Talent Shortage Drives Academic Partnerships
By Liz Allan - 16 Oct, 2023 - Comments: 0

Universities around the world are forming partnerships with semiconductor companies and governments to help fill open and future positions, to keep curricula current and relevant, and to update and expand skills for working engineers. Talent shortages repeatedly have been cited as the number one challenge for the chip industry. Behind those concerns are several key drivers, and many more dom... » read more

Patterning With EUV Lithography Without Photoresists
By Technical Paper Link - 12 Oct, 2023 - Comments: 0

A technical paper titled “Resistless EUV lithography: photon-induced oxide patterning on silicon” was published by researchers at Paul Scherrer Institute, University College London, ETH Zürich, and EPFL. Abstract: "In this work, we show the feasibility of extreme ultraviolet (EUV) patterning on an HF-treated Si(100) surface in the absence of a photoresist. EUV lithography is the leading ... » read more

Chip Industry’s Technical Paper Roundup: September 26
By Liz Allan - 26 Sep, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=146 /] More Reading Technical Paper Library home » read more

Leveraging In-Package Wireless Technology To Improve The Thermal Behavior Of 2.5D Chiplet-Based SoP
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on-Package for Hotspot Removal” was published by researchers at Swiss Federal Institute of Technology Lausanne (EPFL) and University of Applied Sciences and Arts of Western Switzerland (HES-SO). Abstract Excerpt "In this work, we propose a new task mapping heuristic that leverages in-package wireless t... » read more

Research Bits: September 11
By Jesse Allen - 11 Sep, 2023 - Comments: 0

Combining digital and analog Researchers from École Polytechnique Fédérale de Lausanne (EPFL) propose integrating 2D semiconductors with ferroelectric materials for joint digital and analog information processing, which could improve energy efficiency and support new functionality. The device uses a 2D negative-capacitance tungsten diselenide/tin diselenide tunnel FET (TFET), which consu... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy