Chip Industry’s Technical Paper Roundup: October 17

Resistless EUV lithography; V2X sidelink communication; analog HW Trojans; SoC timing side channel threat; thin film materials for quantum; nanophotonic modulators in CMOS; ML in FPGA EDA tool dev; open quantum HW ecosystem.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
Resistless EUV lithography: photon-induced oxide patterning on silicon Paul Scherrer Institute, University College London, ETH Zürich, and EPFL
V2X Sidelink Localization of Connected Automated Vehicles CNR-IEIIT and WiLabCNIT (Italy)
DeMiST: Detection and Mitigation of Stealthy Analog Hardware Trojans Tennessee Tech University and Technische Universitat Wien
A New Security Threat in MCUs – SoC-wide timing side channels and how to find them University of Kaiserslautern-Landau and Stanford University
Thin Film Materials for Room Temperature Quantum Applications Marquette University
Metal-Optic Nanophotonic Modulators in Standard CMOS Technology MIT
Application of Machine Learning in FPGA EDA Tool Development University of Texas Dallas
Open Hardware in Quantum Technology Unitary Fund, Qruise, Technical University of Valencia, M-Labs Limited, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Laboratories, IQM Quantum Computers, PASQAL, Quantonation, Michigan State University, Università di Camerino, Microsoft Quantum, and University of California Berkeley

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