Chip Industry Technical Paper Roundup: Oct. 7


New technical papers recently added to Semiconductor Engineering’s library: [table id=480 /] Find more semiconductor research papers here » read more

CDI For The Metrology Of Copper Pads Used In Hybrid Bonding (Paul Scherrer Institute, Samsung)


A new technical paper titled "Coherent diffractive imaging simulations for wafer inspection of periodic structures" was published by researchers at the Paul Scherrer Institute and Samsung. Excerpt "We present a study of phase retrieval algorithms applied to the metrology of copper pad topography for hybrid bonding. We demonstrate that by including a priori information in the update functi... » read more

Chip Industry Technical Paper Roundup: Apr. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=424 /] Find more semiconductor research papers here. » read more

Differences In The Lithographic Impact Of Particles On The Pellicle Surface Depending On Type Of EUV Mask Pattern


A new technical paper titled "Impact of Sn Particle-Induced Mask Diffraction on EUV Lithography Performance Across Different Pattern Types" was published by Hanyang University and Paul Scherrer Institute. Abstract "This study investigates the differences in the lithographic impact of particles on the pellicle surface depending on the type of extreme ultraviolet (EUV) mask pattern. Using a... » read more

Research Bits: Aug. 20


EUV mirror interference lithography Researchers from the Paul Scherrer Institute developed an EUV lithography technique that can produce conductive tracks with a separation of just five nanometers by exposing the sample indirectly rather than directly. Called EUV mirror interference lithography (MIL), the technique uses two mutually coherent beams that are reflected onto the wafer by two id... » read more

Research Bits: Aug. 13


3D X-ray of chip interiors Researchers from the Paul Scherrer Institute, EPFL Lausanne, ETH Zurich, and the University of Southern California used X-rays to take non-destructive, three-dimensional images of the inside of a microchip at 4 nanometer resolution. To create the images, the researchers relied on a technique called ptychography, in which a computer combines many individual images ... » read more

Metrology And Inspection For The Chiplet Era


New developments and innovations in metrology and inspection will enable chipmakers to identify and address defects faster and with greater accuracy than ever before, all of which will be required at future process nodes and in densely packed assemblies of chiplets. These advances will affect both front-end and back-end processes, providing increased precision and efficiency, combined with a... » read more

Chip Industry Week in Review


Okinawa Institute of Science and Technology proposed a new EUV litho technology using only four reflective mirrors and a new method of illumination optics that it claims will use 1/10 the power and cost half as much as existing EUV technology from ASML. Applied Materials may not receive expected U.S. funding to build a $4 billion research facility in Sunnyvale, CA, due to internal government... » read more

Chip Industry’s Technical Paper Roundup: October 17


New technical papers added to Semiconductor Engineering’s library this week. [table id=155 /] More Reading Technical Paper Library home » read more

Patterning With EUV Lithography Without Photoresists


A technical paper titled “Resistless EUV lithography: photon-induced oxide patterning on silicon” was published by researchers at Paul Scherrer Institute, University College London, ETH Zürich, and EPFL. Abstract: "In this work, we show the feasibility of extreme ultraviolet (EUV) patterning on an HF-treated Si(100) surface in the absence of a photoresist. EUV lithography is the leading ... » read more

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