Chiplets for radar applications; scaling high-performance nanoribbon transistors; wafer inspection; MPC-based distributed trust architecture; Spectre-BTI attack; FPGA architecture enabling concurrent LUT, adder chain usage; rapid ID of defective chips.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage | Nanyang Technological University, Cornell University, Altera, University of Waterloo, University of Toronto |
| Leveraging Modularity of Chiplets to Form a 4×4 Automotive FMCW-Radar in an eWLB-Package | Ruhr University Bochum, Fraunhofer Institute, University Bremen, Infineon, WavesenseDD GmbH |
| Scaling High-Performance Nanoribbon Transistors | Stanford University, HORIBA Scientific, SLAC National Accelerator Laboratory |
| Coherent diffractive imaging simulations for wafer inspection of periodic structures | Paul Scherrer Institute, Samsung |
| Towards efficient wafer visual inspection: Exploring novel lightweight approaches for anomaly detection and defect segmentation | Fraunhofer Portugal AICOS |
| Ultra-wide-field imaging Mueller matrix spectroscopic ellipsometry for semiconductor metrology | Samsung |
| AuthenTree: A Scalable MPC-Based Distributed Trust Architecture for Chiplet-based Heterogeneous Systems | University of Central Florida, Louisiana State University |
| VMSCAPE: Exposing and Exploiting Incomplete Branch Predictor Isolation in Cloud Environments | ETH Zurich |
Find more semiconductor research papers here
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