Blog Review: Oct. 29

By Ed Sperling - 29 Oct, 2014 - Comments: 0

Ansys' Bill Vandermark uncovers the top engineering articles for the week. Check out the tractor beam in Australia that can push and pull objects and Naim's soundbar that may act like a gateway drug to bankruptcy. It may sound counterintuitive, but ARM's Jakub Lamik draws a direct link between bandwidth consumption and power consumption and explains that's the case. Samsung's Farhad Tab... » read more

2.5D Timetable Coming Into Focus

By Ed Sperling - 23 Oct, 2014 - Comments: 0

After years of empty promises, the timetable for [getkc id="82" kc_name="2.5D"] is coming into better focus. Large and midsize chipmakers are behind it, real silicon is being developed, and contracts are being signed. That doesn't mean all of the pieces are in place or that market uptake is at the neck of the hockey stick. And it certainly doesn't mean the semiconductor industry is going to ... » read more

Why Is My Device Better Than Yours?

By Ed Sperling - 23 Oct, 2014 - Comments: 0

Differentiation is becoming a big problem in the semiconductor industry with far-reaching implications that extend well beyond just chips. The debate over the future of [getkc id="74" comment="Moore's Law"] is well known, but it's just one element in a growing list that will make it much harder for chip companies, IP vendors and even software developers to stand out from the pack. And withou... » read more

Changing The World, One Transaction At A Time

By Mike Gianfagna - 23 Oct, 2014 - Comments: 0

It’s the season for foundry seminars. A few weeks ago, eSilicon exhibited at the TSMC Open Innovation Platform event in San Jose. This week, we were at the GLOBALFOUNDRIES Technical Seminar, also in San Jose. I talked with a lot of folks during both events – recited the elevator pitch many times (“who is eSilicon?”). Everybody has attention deficit disorder on a tradeshow floor. Fast ex... » read more

More Than Moore

By Ed Sperling - 01 Oct, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at [getentity id="22664" e_name="Open-Silicon"]; Patrick Soheili, vice president and general manager of IP Solutions at [getentity id="22242" e_name="eSilicon"]; Brandon Wang, engineering group director at [getentity id="22032" e_name="Cadenc... » read more

Blog Review: Oct. 1

By Ed Sperling - 01 Oct, 2014 - Comments: 0

Cadence's Richard Goering writes about a pair of IEEE working groups that are focused on standardizing ways to lower power of software and firmware. The importance of this effort is huge. Mentor's J. VanDomelen looks at the use of 3D printers in outer space. This is a new chapter in manufacturing custom parts in extreme environments. Synopsys' Mick Posner gets an unexpected answer to a ro... » read more

The Real Numbers: Redefining NRE

By Ed Sperling - 26 Sep, 2014 - Comments: 0

Developing ICs at the most advanced nodes is getting more expensive, but exactly how much more expensive is the subject of debate across the semiconductor industry. There are a number of reasons for this discrepancy. Among them: As design flows shift from serial to parallel, it's hard to determine which groups within companies should be saddled with different portions of the bill. The re... » read more

Time To Market Concerns Worsen

By Ed Sperling - 25 Sep, 2014 - Comments: 1

Time to market has always been an issue for chipmakers in highly competitive sectors, but as complexity of chips continues to grow at advanced nodes, and as markets shift increasingly toward consumer electronics, it has jumped to the No. 1 concern. Interviews with engineers at multiple levels inside of some of the largest and midsize chipmakers, conducted by Semiconductor Engineering over th... » read more

Quantifying IP Entitlement For 14/16nm Technologies

By eSilicon - 24 Sep, 2014 - Comments: 0

The scaling benefits of [getkc id="74" comment="Moore"s Law"] are being seriously tested at 28nm. It is no longer a given that the cost per gate will go down at leading edge process nodes below 28nm, e.g., 20nm though 14nm. Rising design and manufacturing costs are contributing factors to this trend. Meanwhile, the competing trend of fewer but more complex [getkc id="81" comment="SoC"] (So... » read more

Changing The IP Supplier Paradigm

By Brian Bailey - 17 Sep, 2014 - Comments: 0

Semiconductor Engineering sat down with Rich Wawrzyniak, senior market analyst for ASIC and SoC at Semico Research; John Koeter, vice president of marketing for the Solutions Group at [getentity id="22035" e_name="Synopsys"]; Mike Gianfagna, vice president of marketing for [getentity id="22242" e_name="eSilicon"]; Peter McGuinness, director of technology marketing at [getentity id="22709" e_nam... » read more

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Knowledge Centers
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