More Than Moore

Experts at the table, part 3: Making IP sticky; three phases of IP development; who will be the first to push into stacked die and why.


Semiconductor Engineering sat down to discuss the value of feature shrinks and what comes next with Steve Eplett, design technology and automation manager at Open-Silicon; Patrick Soheili, vice president and general manager of IP Solutions at eSilicon; Brandon Wang, engineering group director at Cadence; John Ferguson, product manager for DRC applications at Mentor Graphics; and Kevin Kranen, director of strategic alliances at Synopsys. What follows are excerpts of that conversation. Part one can be found here. Part two can be found here.

SE: As we push into stacked die, one of the problems is that costs and silos need to be restructured. How does this get solved?

Soheili: It’s our challenge. Supply chain management doesn’t stop with calling up the EDA and foundry and IP guys. It’s solving those issues and being able to create a complete solution, guaranteed to work, and we’re going to take care of the application costs. This is our business model.

Kranen: It used to be the IDMs that did that, but there aren’t so many of them anymore. It’s the supply chain and the infrastructure. The foundries are taking baby steps in to make sure it’s safe, but the whole ecosystem has to pull through.

Soheili: Most of our time is spent vetting the infrastructure for and manageability and all the costs and risks associated with it. We’re fighting patents on testability and manufacturability. We’re dealing with how to solve signal integrity issues in a way that hasn’t been contemplated before.

Eplett: The internal costs we’ve discussed because they’re our issues. But whenever we talk to a potential partner about a third-party die, we don’t get more than five minutes into a conversation before they want to know, ‘If the integrated die fails, how do you handle that?’ We determine who owns debug. Reliability failures consume more of the conversation than technical aspects. We don’t have an answer for some of these questions, and you can’t build a business if you don’t.

SE: How much of this moves to subsystems and platforms rather than buying IP blocks and integrating them together?

Ferguson: My customers want all of the above.

Kranen: It depends on where your product is in the curve. In the mobile market, at the low end, there are integrated platforms and they’re willing to take whatever the next guys takes and differentiation is not so important. At the high end of the handset or mobile market, you really want to differentiate and you’re willing to pay extra and go discrete and not worry about the integrated platform.

SE: Markets are becoming fragmented, and SoCs may vary by country and what they’re connected to. It becomes much harder to achieve economies of scale.

Soheili: Geopolitics now plays a role in product selection.

Kranen: That’s always been there to some extent because of the phone companies.

Soheili: We saw this trend showing up three to four years ago with OEMs that either had a large market they were serving or a large enough stake in their markets, meaning they were shipping a high-end unit and needed to differentiate their products. If your shows up in another product then you lose your market share, because someone is always willing to take less margin, and at the end of the day in the consumer game it’s all about margin and your distribution channel. That trend is now at full throttle. As many starts as there are these days, there are even more right behind those inside these large OEMs. Everybody is working on a custom chip and looking into differentiating at the chip level as well as the software level. It’s not just the software.

SE: How much of this comes down to customized versions of standard IP?

Kranen: You don’t win by making non-standard standard IP. That’s the way you get to the broadest market base and have the greatest success. Occasionally we do custom IP, but that costs more. Sometimes people ask for non-standard, and we try not to do it, but sometimes you have to in order to win the business.

Wang: We look at IP in three stages. The first stage was in the 1990s, when the fabless model was just coming about. There were a lot of mom-and-pop shops. Then it went to an IP bazaar type of market for five or six years. Now we look at IP from the standpoint of an IP factory. There are two sides of making IP standard. If it’s a standards-based IP, that means it is a very broad market. It’s a standard market, so it’s less sticky. The question here is the acquisition cost—the development cost and the sales cost. The amount of revenue is based on how sticky the IP is. Will you have it for three years? Five years? Non-standards-based IP is very sexy. You can take a customer and count on continuous revenue. With SoCs, there are so many standards-based IP that the challenge is to make it not-so-standard so that you can have access to the market you want but still have enough stickiness. That’s the Holy Grail. And that’s why I call it an IP factory. You start with standards-based IP and add things to create stickiness and help customers differentiate.

Kranen: Our view is that stickiness comes from the quality and being silicon-proven. There were three or four generations of USB. It was about making each generation better. We consider the stickiness to smaller and better.

SE: When are we going to start seeing significant changes? Is there even room for a step-function anymore?

Soheili: I was at an IEEE conference recently where the discussion was all about the IP factory context. You design things for market. You design them for stickiness. As integrators, we are absolutely reliant on that. If anyone slows down, the whole industry will collapse. Where we come into play with our IP is that we either get the rights to modify IP from other vendors, where we can add more stickiness to it, or we design our own and use it only when it’s needed. It’s expensive. But because of the end value that we get from our customer base, which is the chip itself, the ROI calculation is a little bit different. It’s not just licensing the IP. It’s the annuity from the chip. We see it from a different economic standpoint. So customization and optimization of standards-based products from IP factories is absolutely critical where you need stickiness or differentiation. As far as a step function, it’s evolution. You won’t see Moore’s Law going away overnight. It will take generations. We’ll see experimentation in different markets.

Eplett: The cost conversations with customers these days are placeholders for some vendors. When we came up with our test chip we had 50 companies that wanted to kick the tires. After four weeks, the only ones that came back were the people who had to have the performance it brought. Eventually we had small conversations with other people, but it’s not today.

Kranen: You’ll see a bunch of sweet spots where there will be evolution for that kind of packaging configuration. You’ll see the continued use of interposers. You might see package-on-package eventually evolving into some other kind of packaging for the mobile markets. But it will be driven in specific areas where the architecture of the interconnect really fits that application well and the cost factor is covered by the dollars you can get for it, or it really is a cheaper solution.

Wang: 2.5D and 3D are really in phase one. You have a system design or chip design, and that’s where 2.5D and fit. Maybe networking will use 2.5D for performance. The second phase is where the step function happens. Instead of looking at the system design and seeing if the technology fits, you look at the technology and question whether you can redefine your system architecture and take advantage of that. You already know the connection is Wide I/O. Now you add it into the assembly process. What I’m seeing is that you need to completely redefine the SoC where you may pull flash memory out of the SoC and put it on another die. You route your clock tree from the bottom die up to the top die and back down. If you have trouble closing timing, you should be able to route the signal up from chip A to chip B in a very short pass in the same way that people handle in an SoC right now. That’s a step function in technology and redefining the architecture. When that becomes an option for the whole design community, that’s where we’ll see a big movement. It won’t just be Wide I/O as a memory interface. It will be everywhere.

Kranen: There’s a tricky balancing equation, though, with cost.

Ferguson: Ultimately it comes down to who’s going to be first. You have to take a risk. So either you have a dramatic reduction in cost or you have availability to a market that you don’t have now. You kick somebody else out. It’s a big risk proposition. You won’t go there unless you’re desperate or you have extra money to spend or you don’t have another choice. Who wants to be the first one doing this with RF analog components? You don’t want to be the first one unless you have to. Someone eventually will do it and, if they’re successful, others will follow. That’s what we’re seeing in each of these markets.

Eplett: The market for 2.5D is there, but it’s out in the distance.

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