tag: eSilicon

When Will 2.5D Cut Costs?
By Brian Bailey - 07 Aug, 2014 - Comments: 2

There is a constant drive to reduce costs within the semiconductor industry and, up until now, [getkc id="74" comment="Moore's Law"] provided an easy path to enable this. By adopting each smaller node, transistors were cheaper, but that is no longer the case, as explained in a recent article. The industry will need to find new technologies to make this happen and some people are looking towards... » read more

Changing The IP Supplier Paradigm
By Brian Bailey - 07 Aug, 2014 - Comments: 1

Just a few years ago, the [getkc id="43" comment="Intellectual Property"] (IP) business consisted of small blocks being sold by small companies and an almost over the wall delivery mechanism. The industry quickly realized the problems with this supply chain and the IP business went through very rapid change. At the same time, the average size of the IP blocks has increased and today, what we th... » read more

Blog Review: July 30
By Ed Sperling - 30 Jul, 2014 - Comments: 0

Mentor’s Colin Walls looks at a free collaborative online tool called codepad, which can be used for compiling, interpreting and executing code quickly. Free is good—sometimes. Cadence’s Brian Fuller followed a recent panel on high-speed, cross-fabric interface design, which focused on why designers need to consider chip, package and board to ensure signal and power integrity. So what... » read more

IP Integration Challenges Rising
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

It’s not just [getkc id="80" comment="lithography"] that is putting a crimp in sub-28nm designs. As more functions, features, transistors and software are added onto chips, the pressure to get chips out the door has forced chipmakers to lean more heavily on third-party IP providers. Results, as you might expect, have been mixed. The number of blocks has mushroomed, creating its own web of ... » read more

EDA’s Hedge Plays
By Ed Sperling - 24 Jul, 2014 - Comments: 0

While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

New Winners And Losers
By Brian Bailey - 24 Jul, 2014 - Comments: 0

During DAC 2013, Robert Colwell of DARPA said he was attempting to prepare the U.S. Dept. of Defense for what he believes is the cataclysm caused by the end of [getkc id="74" comment="Moore's Law"]. He asked the question, “What happens when we don’t have a new technology that doubles the number of transistors every couple of years?” Colwell believes that power is the primary reason why... » read more

2.5/3D IC – Do We Have Liftoff?
By Mike Gianfagna - 24 Jul, 2014 - Comments: 2

The challenges of Moore’s law scaling at advanced technolgy nodes are well documented. I won’t repeat them here. The benefits of “more than Moore” scaling (i.e., 2.5D and 3D ICs) are also well-known. This technology has shown great promise to provide an alternate path for large-scale integration. The technology has seen a lot of research effort, infrastructure support, standards develop... » read more

Foundries Versus OSATs
By Ed Sperling - 24 Jul, 2014 - Comments: 2

Since the 1990s, commercial foundries have ruled semiconductor manufacturing while the [getkc id='83' comment='OSAT'] providers (OSATs) have dominated IC packaging and testing. But as the industry moves toward stacked die over the next couple of years, and big foundries see a chance to expand their reach, the stage is set for an all-out war. There is much at stake on both sides. Foundries g... » read more

Blog Review: July 2
By Ed Sperling - 02 Jul, 2014 - Comments: 0

Mentor’s Nazita Saye has reservations about driverless cars. Sometimes it’s actually fun to drive—and sometimes it isn’t. Cadence’s Brian Fuller is a bit more optimistic about driverless cars. He says that from the standpoint of safety, efficiency and environment, autonomous vehicles will be a big step forward—if and when some critical problems are solved. And along the same... » read more

The Week In Review: Design
By Ed Sperling - 27 Jun, 2014 - Comments: 0

Tools eSilicon uncorked a GDSII online quote system for TSMC, which allows chipmakers to pick a variety of information ranging from process technology to package to yield and tapeout and production forecast and get a quote within minutes. This is a new twist in the value chain provider market. Synopsys added program to speed up FPGA-based prototype creation, which includes approved third-pa... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy