Foundries Versus OSATs

As the industry migrates to 2.5D and 3D, a turf war is brewing.

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Since the 1990s, commercial foundries have ruled semiconductor manufacturing while the Outsourced Semiconductor Assembly and Test providers (OSATs) have dominated IC packaging and testing. But as the industry moves toward stacked die over the next couple of years, and big foundries see a chance to expand their reach, the stage is set for an all-out war.

There is much at stake on both sides. Foundries generate about 40% to 45% margins, while OSATs generate about 20% to 25%, according to Jim Walker, research vice president for semiconductor manufacturing at Gartner. For the foundries, this is a potential land grab while safeguarding their home turf.

The story is worse for the OSATs, however, because they’ve been seeing price erosion of 2% to 5% per year. Moreover, the up-front investment on the foundry equipment side is much higher than for the OSATs, making the cost of entry for OSATs to get into the foundry side prohibitive, while the foundries looking to get into the OSAT world are scrambling to ramp up their expertise.

But there also is very high motivation on the part of the OSATs to win a piece of this business. “The OSATs are hungry to gain this business,” said Walker. “If they can get to 40% to 45% margins, their profits will increase.”

That may explain why William Chen, senior technical advisor at ASE Group was so upbeat on new packaging approaches. “[System in packge] is an important trend,” he said. “The economic benefit of Moore’s Law is receding. Packaging has been moving in lock step with that.”

There are a lot of OSATs vying for that business—about 150 of them, according to Gartner’s numbers. ASE Group, with 19% market share, is the largest OSAT, followed by Amkor with a 12% market share. In contrast, there are only a handful of large foundries, and TSMC controls roughly 50% of the market, followed by GlobalFoundries with 11% and UMC with 10%.

Where the battles will be fought
What makes this confrontation possible and very real is the insertion point for through-silicon vias. While the foundries control the front end of the manufacturing, the OSATs dominate the back end with test and packaging. And that’s where the TSVs may be best inserted—although there isn’t enough data yet to say this is the best and only choice.

Still, this is where the fight likely will take place, which is squarely in the OSATs’ backyard. The middle end of line is where the backgrinding, etching, copper revealing, wafer bumping and temporary bonding are done. The move by big foundries such as TSMC, Intel and Samsung into these segments—and the alliances of GlobalFoundries, SMIC and UMC with the OSATs in these sectors—will pit the biggest foundries against an alliance of specialized expertise. And while it’s unlikely that any single company will take all, it is likely to create a price war that will make stacked die much more affordable to the rest of the semiconductor industry.

“There are advantages to both approaches,” said Ramakanth Alapati, director of package architecture and customer technology at GlobalFoundries. “The foundries control the back end of the supply chain, which helps with time to market. We let the OSATs control the middle end of the line. The traditional OSATs have come up to speed with a fair degree of sophistication, too. People have been talking about a gap between the captive supply chain and the non-captive supply chain, but in our opinion it’s non-existent.”

However, Alapati emphasized that no two OSATs are the same. Their capabilities need to be understood in detail. “We work with different OSATs for different products, depending on their strength.”

Most of the OSATs are scattered in China, Korea, Taiwan and Singapore, and to a lesser extent the United States. They utilize a different business model that leverages more depreciated equipment and capacity. From a business standpoint, that raises questions about how effectively they can compete with large foundries if they have to invest in some of the same very expensive equipment.

It’s all business
Still, business issues have proved to be one of the biggest hurdles to stacked die going mainstream, not technology or tools. There’s nothing to preclude a stacked die from including a 28nm FD-SOI chip or a 16/14nm FPGA coupled with an older-generation MEMS chip and a Hybrid Memory Cube—all of which can be packaged together relatively simply in a 2.5D IC configuration.

“One of the biggest challenges is business,” said Mike Gianfagna, vice president of marketing at eSilicon. “It’s a question of who takes the yield risk and the inventory risk. There are still technical issues and standards issues, but the bigger challenge is managing a broad supply chain. Part of the value-add is coordinating between suppliers, managing those suppliers, the inventory, the substrate for the stacked die, making sure it all gets delivered on time and with good yield.”

He said that TSMC is trying to win the whole project, but to do so it needs to add a very specific set of technologies, which until recently has included a silicon interposer and a fixed Wide I/O stack. “The reality is there are multiple ways to deal with this, each with their own merits and problems. The market will resist homogenization, and with a growing market to say that it all will be served by two or three foundries is not the likely outcome.”

That seems to be a common thread among design and implementation services companies such as eSilicon, Open-Silicon, and a host of startups sprouting up in India and China—along with keeping cost to a minimum, adding flexibility into the design wherever possible, and being able to leverage whichever foundry can offer the best technologies, pricing and packaging.

“The fabs will have the upper hand in putting these together, because they have the machinery and the know-how,” said Taher Madraswala, president of Open-Silicon. “We’re aligned with GlobalFoundries and TSMC on this, but we also see an increasing emphasis on passive interposers—wires and vias that may have a buffer on the wires and bias with voltage. Eventually we may see more active interposers, too. Whoever provides the most economical solution, we will line up with them.”

Experimentation expands
That is one of the big questions: Who can provide the most economical solution. So far there isn’t enough data to make comparisons, but at least for the time being the foundries appear to have the upper hand.

“Intel, Samsung and TSMC have a much better handle on how to do stacked die with fewer yield issues,” said Joanne Itow, managing director for manufacturing at Semico Research. “They all have their own technologies. But they also still have a lot to learn, and this is not an inexpensive proposition.”

Itow said the OSATs are installing capacity and are increasing their R&D. She noted the next step is to beef up their process technology.

And at the very least, the next few years should prove healthy for equipment makers, EDA tool providers and for new investment throughout the semiconductor industry. With the economics of Moore’s Law looking increasingly shaky after 14/16nm, investment is now a requirement. What comes out of that investment remains to be seen, but it seems pretty clear that a war will be fought as companies stake their claims on future possibilities.