Ready To Pounce

Companies are sitting on sidelines, poised to jump on the bandwagon once it gets rolling.

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A series of inflection points at 16/14nm and beyond is having a rather unusual effect on the semiconductor industry. Rather than forge ahead with the next nodes to gain an edge and early lead over rivals—the standard formula for success over the past five decades—the entire supply chain is poised on the edge, waiting for someone to make the first move before they take action.

The problem isn’t just one of being the first mover this time. It’s being the first mover in the right direction, because it’s too costly to charge down every direction at once. So while companies have taken steps to assure they can move quickly in any direction, they’re not fully committed to any one.

Big foundries have largely developed their process technology for 16/14nm and 10nm, most are only ramping up partial capacity until they see where their competitors will hang their hat. It’s quite possible, for example, that if GlobalFoundries, Samsung, Intel commit to building massive capacity at 14nm at the expense of 10nm, TSMC may opt to put most of its effort into 10nm. And GlobalFoundries and Samsung are watching what TSMC is doing to make sure they don’t get leapfrogged, while also peeking over their shoulders at Intel, UMC, SMIC, and remaining deeply engaged in dialog with the large OEMs that can fill their fabs. In the finFET world, everything is in limbo.

At the same time, all three of them have stepped up efforts around 2.5D and 3D ICs. GlobalFoundries, UMC and TSMC have invested in interposer technology, while Samsung has invested in 3D memory.

It’s a standoff, but one that will end very suddenly at some point in the next 12 to 24 months with an outlay that likely will run tens of billions of dollars in equipment, process development, IP qualification, packaging know-how and hiring of workers with deep expertise in these areas.

The OSATs—led by ASE, Amkor and STATS ChipPAC—are ramping up their own expertise in 2.5D process technology and test. TSMC has said publicly it wants to hit $2 billion in packaging revenues, up from what industry sources say is currently about $800 million. That can only be done with a massive push into stacked die, observers say. This is one sector that has no choice but to heavily invest in tooling and expertise, because while foundries such as TSMC may be newcomers in this area—the so-called middle end of line, home to backgrinding, etching, copper revealing, wafer bumping and temporary bonding—they also have much deeper pockets than the OSATS.

All of this leaves EDA sitting on the fence in several key areas. First, complexity is forcing them to work more closely with all foundries and OSATs and their customers, meaning a deeper commitment on each of these potential directions. Second, it leaves them in doubt about where to throw their efforts in new tooling, such as pathfinding or simply migrating existing tools to new and unique processes. And third, it forces them to choose sides to some extent because not everyone will win at this game—despite the company line that all EDA vendors have to work with everybody. In a highly complex world of 16/14nm and 10nm chips, it simply can’t be done.

Choices will be required for economic survival, and that should make for some interesting bets being placed by EDA vendors, as well.