tag: eSilicon

Moore’s Law Tail No Longer Wagging The Dog
By Brian Bailey - 26 Jun, 2014 - Comments: 3

In a recent special report titled “Will 7nm and 5nm really happen?” Semiconductor Engineering outlined the progress being made for new production nodes and the progress being made to overcome the technological challenges that they contain. But who are the likely candidates for those new nodes and who is going to pay for their development, including the EDA tools that will be necessary to ut... » read more

Can EDA Keep Growing?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Slower progress at the leading edge of process technology, coupled with rising costs and fewer design starts, are changing the economics of the EDA world. Not surprisingly, there is almost a direct correlation between the shrinking number of startups in the field and the number of customers working on the most advanced nodes. So what exactly does this mean for the EDA world? Big changes, for... » read more

Semiconductor Self-Service: The Next Wave
By Mike Gianfagna - 26 Jun, 2014 - Comments: 0

The Internet is a marvelous invention. We all know it can bring a universe of human knowledge to our desktop. Thanks to some clever technology produced by some very successful companies, you also can browse all this information in real time, learning and discovering all the way. This ability to learn and discover is particularly interesting from a business perspective. It has created a truly... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

Tougher Memory Choices
By Brian Bailey - 23 Jun, 2014 - Comments: 1

In part 1 of this roundtable, the participants talked about the investments being made in memory technologies, the role that memories play in system security and the tools support for optimizing memory architecture. Taking part in the conversation are Herbert Gebhart vice president of interface and system solutions in the Memory and Interfaces Division of Rambus, Bernard Murphy, chief technolog... » read more

Tougher Memory Choices
By Brian Bailey - 12 Jun, 2014 - Comments: 1

Memories have become a hot topic, so Semiconductor Engineering sat down with experts during DAC to discuss some of the issues. Taking part in the conversation were Herbert Gebhart vice president of interface and system solutions in the Memory and Interfaces Division of Rambus, Bernard Murphy, chief technology officer for Atrenta; Patrick Soheili, vice president and general manager for IP Soluti... » read more

Blog Review: June 11
By Ed Sperling - 11 Jun, 2014 - Comments: 0

eSilicon’s Jack Harding says that EDA and semiconductors need to focus heavily on recruiting the next generation of brilliant engineers. This technology is cool, and even better it makes all the other cool technology work. It’s time to remind the rest of the world. Cadence’s Brian Fuller distills a panel discussion at DAC on computer vision—the sensors that enable driverless cars, a... » read more

Self-Service Comparisons Come To SoC Design
By Ann Mutschler - 23 May, 2014 - Comments: 0

Under the guise of enabling self-service comparison of its compilable memories and providing self-service online quoting of TSMC technology, semiconductor design and manufacturing services provider eSilicon Corp. detailed the latest evolution of its business model—and one that could have interesting implications for the IP and memory markets. This move reflects the changing dynamics of cus... » read more

Tech Talk: The New Cost Per Gate Equation
By Ed Sperling - 22 May, 2014 - Comments: 1

eSilicon's Javier DeLaCruz talks with Semiconductor Engineering about new types of interposers, why just shrinking features is doomed, and what progress has been made in building 2.5D chips. [youtube vid=akj8r8nNktM] » read more

New Business Model: Flexible Silos
By Ed Sperling - 22 May, 2014 - Comments: 0

Operational silos within organizations have a long history of streamlining processes and maximize efficiency. In fact, that approach has made enterprise resource planning applications a must-have for most companies, and cemented the fortunes of giants such as SAP and Oracle, as well as the giant consulting companies that recommend them. But those kinds of delineations don’t work so well fo... » read more

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