tag: etch

Research Bits: Feb. 18
By Jesse Allen - 18 Feb, 2025 - Comments: 0

Predicting band gap with neural networks Researchers from Kyoto University developed a machine learning model to predict the band gap of novel semiconductor materials. Using data from almost 2,000 semiconductor materials, the team tested six different neural networks. They found that the incorporation of conditional generative adversarial networks (CGAN) and message passing neural networks ... » read more

Research Bits: Feb. 10
By Jesse Allen - 10 Feb, 2025 - Comments: 0

Speeding up 3D NAND etch Researchers from Lam Research, the University of Colorado Boulder, and Princeton Plasma Physics Laboratory (PPPL) investigated ways to speed up the cryogenic reactive ion etching process for 3D NAND by using a combined hydrogen fluoride gas to create the plasma. “Cryo etch with the hydrogen fluoride plasma showed a significant increase in the etching rate compared... » read more

Using Dummy Patterning To Solve Etch Uniformity Problems
By James Kim - 21 Nov, 2024 - Comments: 0

Semiconductor devices are made up of hundreds of thin layers of materials stacked by multiple deposition and etch processes. Process engineers need to design the best combination of deposition and etch processes to ensure uniformity across an entire chip area and across the silicon wafer. Uniformity is the most common and critical parameter that is monitored in semiconductor fabrication, especi... » read more

Optimizing Wafer Edge Processes For Chip Stacking
By Laura Peters - 23 Sep, 2024 - Comments: 0

Stacking chiplets vertically using short and direct wafer-to-wafer bonds can reduce signal delay to negligible levels, enabling smaller, thinner packages with faster memory/processor speeds and lower power consumption. The race is on to implement wafer stacking and die-to-wafer hybrid bonding, now considered essential for stacking logic and memory, 3D NAND, and possibly multi-layer DRAM stac... » read more

Single Vs. Multi-Patterning Advancements For EUV
By Gregory Haley - 20 Jun, 2024 - Comments: 0

As semiconductor devices become more complex, so do the methods for patterning them. Ever-smaller features at each new node require continuous advancements in photolithography techniques and technologies. While the basic lithography process hasn’t changed since the founding of the industry — exposing light through a reticle onto a prepared silicon wafer — the techniques and technology ... » read more

Understanding CFETs, A Next Generation Transistor Architecture
By Sam Sarkar - 23 May, 2024 - Comments: 0

Computing power has experienced exponential growth over the last 70 years. This has largely been achieved through transistor scaling. Due to a continuous reduction in the size of transistors, engineers have been able to pack more and more of them onto a single chip [1]. This has led to faster, more powerful, and more energy-efficient devices. Improvements in fabrication processes and materials,... » read more

Semiconductor Device Manufacturing Process Challenges And Opportunities
By Andreas Bier - 07 Dec, 2023 - Comments: 0

Semiconductor device manufacturing involves a complex series of processes that transform raw materials into finished devices. The process typically involves four major stages: wafer fabrication, wafer testing, assembly or packaging, and final testing. Each stage has its own unique set of challenges and opportunities. The semiconductor device manufacturing process faces several challenges, inclu... » read more

When And Where To Implement AI/ML In Fabs
By Anne Meixner - 21 Sep, 2023 - Comments: 0

Deciphering complex interactions between variables is where machine learning and deep learning shine, but figuring out exactly how ML-based systems will be most useful is the job of engineers. The challenge is in pairing their domain expertise with available ML tools to maximize the value of both. This depends on sufficient quantities of good data, highly optimized algorithms, and proper tra... » read more

Improving Gate All Around Transistor Performance Using Virtual Process Window Exploration
By Sumant Sarkar - 25 Jul, 2023 - Comments: 0

As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar transistor architectures toward 3D devices. Gate-all-around (GAA) architectures are an example of this type of 3D device [2]. In a GAA transistor, the gate oxide surrounds the channel in all directions.... » read more

Etch Processes Push Toward Higher Selectivity, Cost Control
By Laura Peters - 18 May, 2023 - Comments: 0

Plasma etching is perhaps the most essential process in semiconductor manufacturing, and possibly the most complex of all fab operations next to photolithography. Nearly half of all fab steps rely on a plasma, an energetic ionized gas, to do their work. Despite ever-shrinking transistor and memory cells, engineers continue to deliver reliable etch processes. “To sustainably create chips... » read more

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