tag: ETH Zurich

Circuit knitting Based On Quasiprobability Simulation
By Technical Paper Link - 10 May, 2022 - Comments: 0

New paper "Circuit knitting with classical communication, " from researchers at ETH Zurich and IBM Quantum. Abstract: "The scarcity of qubits is a major obstacle to the practical usage of quantum computers in the near future. To circumvent this problem, various circuit knitting techniques have been developed to partition large quantum circuits into subcircuits that fit on smaller devices,... » read more

Research Platform for Heterogeneous Computing (ETH Zurich)
By Technical Paper Link - 09 May, 2022 - Comments: 0

New academic paper from ETH Zurich, "HEROv2: Full-Stack Open-Source Research Platform for Heterogeneous Computing." Abstract: "Heterogeneous computers integrate general-purpose host processors with domain-specific accelerators to combine versatility with efficiency and high performance. To realize the full potential of heterogeneous computers, however, many hardware and software design ... » read more

Week In Review: Manufacturing, Test
By Linda Christensen - 06 May, 2022 - Comments: 0

Acquisitions & Investments California-based MaxLinear plans to acquire Taiwan-based Silicon Motion (SMI), in a cash and stock deal valued at about $3.8 billion. Silicon Motion’s NAND flash controller technology for solid state storage devices, will extend MaxLinear’s RF, analog, and mixed signal portfolio. ISMC will invest about $3 billion in a semiconductor plant in India’s south... » read more

Technical Paper Round-up: May 3
By Linda Christensen - 03 May, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=24 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

A Case for Transparent Reliability in DRAM Systems
By Technical Paper Link - 29 Apr, 2022 - Comments: 0

New technical paper from ETH Zurich and TU Delft. Abstract "Today's systems have diverse needs that are difficult to address using one-size-fits-all commodity DRAM. Unfortunately, although system designers can theoretically adapt commodity DRAM chips to meet their particular design goals (e.g., by reducing access timings to improve performance, implementing system-level RowHammer mitigati... » read more

Academic Research Paper Round-Up: April 13
By Linda Christensen - 13 Apr, 2022 - Comments: 0

The volume of research into advanced semiconductors is rising and widening. The latest batch includes hybrid power-gating architecture, RRAM devices models, improved FMEA, quantum machine learning, enhanced nonlinear optics, harvesting energy after sundown, direct chemisorption-assisted nanotransfer printing, and more. Topping the list of researchers this week are ETH Zurich, Stanford Unive... » read more

DarkGates: A Hybrid Power-Gating Architecture to Mitigate the Performance Impact of Dark-Silicon in High Performance Processors
By Technical Paper Link - 12 Apr, 2022 - Comments: 0

New research paper from ETH Zurich and others. Abstract "To reduce the leakage power of inactive (dark) silicon components, modern processor systems shut-off these components' power supply using low-leakage transistors, called power-gates. Unfortunately, power-gates increase the system's power-delivery impedance and voltage guardband, limiting the system's maximum attainable voltage (i.e., ... » read more

Benchmarking Memory-Centric Computing Systems: Analysis of Real Processing-in-Memory Hardware
By Technical Paper Link - 10 Mar, 2022 - Comments: 0

Abstract "Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bo... » read more

SparseP: Towards Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Systems
By Technical Paper Link - 08 Mar, 2022 - Comments: 0

Abstract "Several manufacturers have already started to commercialize near-bank Processing-In-Memory (PIM) architectures. Near-bank PIM architectures place simple cores close to DRAM banks and can yield significant performance and energy improvements in parallel applications by alleviating data access costs. Real PIM systems can provide high levels of parallelism, large aggregate memory bandwi... » read more

Why RISC-V Is Succeeding
By Brian Bailey - 24 Feb, 2022 - Comments: 5

There is no disputing the excitement surround the introduction of the RISC-V processor architecture. Yet while many have called it a harbinger of a much broader open-source hardware movement, the reasons behind its success are not obvious, and the implications for an expansion of more open-source cores is far from certain. “The adoption of RISC-V as the preferred architecture for many sili... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy