Chip Industry’s Technical Paper Roundup: Oct. 4

RISC-V framework for logic-in-memory; FPGA cybersecurity; DRAM refresh latency; memristors; 6-qubit quantum processor; MXene transistors; fault inspection; thermal ML solver; SPI safety architecture; spin-orbit qubit


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures Politecnico di Torino (Italy), Univerity of Tor Vergata (Italy), and University of Twente (The Netherlands)
A Survey on FPGA Cybersecurity Design Strategies Université Laval, Canada
HiRA: Hidden Row Activation for Reducing Refresh Latency of Off-the-Shelf DRAM Chips ETH Zürich, TOBB University of Economics and Technology and Galicia Supercomputing Center (CESGA)
Self-organization of an inhomogeneous memristive hardware for sequence learning University of Zurich, ETH Zurich, Université Grenoble Alpes, CEA, Leti and Toshiba
Universal control of a six-qubit quantum processor in silicon Delft University of Technology, QuTech and Netherlands Organization for Applied Scientific Research (TNO)
High-throughput design of functional-engineered MXene transistors with low-resistive contacts Indian Institute of Science (IISc) Bangalore
Improving automated visual fault inspection for semiconductor manufacturing using a hybrid multistage system of deep neural networks Chemnitz University of Technology
A single hole spin with enhanced coherence in natural silicon Université Grenoble Alpes, CEA, LETI, and CNRS
A Thermal Machine Learning Solver For Chip Simulation Ansys
FMEDA based Fault Injection to Validate Safety Architecture of SPI (Serial Peripheral Interface) R. V. College of Engineering in India and Analog Devices

Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers.

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