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Technical Paper Round-up: August 8

Transistor benchmarking; chiplet, interposer & SIP supply chain risks; analog DL; RISC-V; GAA; ternary inverter w/memory function; nanowires; reservoir computing w/FeFETs; junctionless FET

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New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
ToSHI – Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance Florida Institute for Cybersecurity (FICS) Research, University of Florida
How to Report and Benchmark Emerging Field-Effect Transistors NIST, Purdue University, UCLA, Theiss Research, Peking University, NYU, Imec, RWTH Aachen, and others
Nanosecond protonic programmable resistors for analog deep learning MIT, IBM Watson AI Lab,
RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs University of Bologna and ETH Zurich
Directed Self-Assembly for Dense Vertical III–V Nanowires on Si and Implications for Gate All-Around Deposition Lund University in Sweden
New ternary inverter with memory function using silicon feedback field-effect transistors Korea University
Polarization-selective reconfigurability in hybridized-active-dielectric nanowires University of Oxford and University of Exeter
Reservoir computing on a silicon platform with a ferroelectric field-effect transistor University of Tokyo
Planar Junctionless Field-Effect Transistor for Detecting Biomolecular Interactions Max Planck Center for Complex Fluid Dynamics, University of Twente, University of Glasgow, and Luxembourg Institute of Science and Technology (LIST)
Detrimental effect of high-temperature storage on sulfide-based all-solid-state batteries Seoul National University, National Synchrotron Radiation Research Center (Taiwan), and Battery Material Lab at the Samsung Advanced Institute of Technology

Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for our global audience. At a minimum, papers need to be well researched and documented, relevant to the semiconductor ecosystem, and free of marketing bias. There is no cost involved for us posting links to papers.



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