Chip Industry Technical Paper Roundup: Feb. 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=187 /] More ReadingTechnical Paper Library home » read more

Technical Paper Roundup: Sept. 12


New technical papers added to Semiconductor Engineering’s library this week. [table id=51 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit f... » read more

Control of the Schottky barrier height in monolayer WS2 FETs using molecular doping (NIST)


A new research paper titled "Control of the Schottky barrier height in monolayer WS2 FETs using molecular doping" was published by researchers at NIST, Theiss Research, Naval Research Laboratory, and Nova Research. Abstract: "The development of processes to controllably dope two-dimensional semiconductors is critical to achieving next generation electronic and optoelectronic devices. Unde... » read more

Technical Paper Round-up: August 8


New technical papers added to Semiconductor Engineering’s library this week. [table id=44 /] Semiconductor Engineering is in the process of building this library of research papers. Please send suggestions (via comments section below) for what else you’d like us to incorporate. If you have research papers you are trying to promote, we will review them to see if they are a good fit for... » read more

Reporting and Benchmarking Process For A 2D Semiconductor FET


New research paper titled "How to Report and Benchmark Emerging Field-Effect Transistors" was published from researchers at NIST, Purdue University, UCLA, Theiss Research, Peking University, NYU, Imec, RWTH Aachen, and others. "Emerging low-dimensional nanomaterials have been studied for decades in device applications as field-effect transistors (FETs). However, properly reporting and compar... » read more

Power/Performance Bits: Jan. 22


Efficient neural net training Researchers from the University of California San Diego and Adesto Technologies teamed up to improve neural network training efficiency with new hardware and algorithms that allow computation to be performed in memory. The team used an energy-efficient spiking neural network for implementing unsupervised learning in hardware. Spiking neural networks more closel... » read more