Chip Industry’s Technical Paper Roundup: August 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=39 /] More Reading Technical Paper Library home » read more

Implementing Fast Barriers For A Shared-Memory Cluster Of 1024 RISC-V Cores


A technical paper titled “Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster” was published by researchers at ETH Zürich and Università di Bologna. "Synchronization is likely the most critical performance killer in shared-memory parallel programs. With the rise of multi-core and many-core processors, the relative impact on performance and energy overhe... » read more

RISC-V Open Platform for Next-Gen Automotive ECUs (ETH Zurich, Huawei)


A technical paper titled “Towards a RISC-V Open Platform for Next-generation Automotive ECUs” was published by researchers at ETH Zurich and Huawei Research Center (Italy). Abstract: "The complexity of automotive systems is increasing quickly due to the integration of novel functionalities such as assisted or autonomous driving. However, increasing complexity poses considerable challenges... » read more

Chip Industry’s Technical Paper Roundup: July 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=119 /] More Reading Technical Paper Library home » read more

Week In Review: Auto, Security, Pervasive Computing


The Biden-Harris Administration announced the U.S. Cyber Trust Mark, a cybersecurity certification and labeling program to help consumers choose smart devices less vulnerable to cyberattacks. The Federal Communications Commission (FCC) is applying to register the Cyber Trust Mark with the U.S. Patent and Trademark Office and it would appear on qualifying smart products, including refrigerators,... » read more

Analog On-Chip Learning Circuits In Mixed-Signal Neuromorphic SNNs


A technical paper titled "Neuromorphic analog circuits for robust on-chip always-on learning in spiking neural networks" was published by researchers at Institute of Neuroinformatics, University of Zurich, and ETH Zurich. Abstract: "Mixed-signal neuromorphic systems represent a promising solution for solving extreme-edge computing tasks without relying on external computing resources. Their s... » read more

Chip Industry’s Technical Paper Roundup: July 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=118 /] (more…) » read more

RowPress: Read-Disturb Phenomenon In DDR4 DRAM Chips


A technical paper titled "RowPress: Amplifying Read Disturbance in Modern DRAM Chips" was published by researchers at ETH Zürich. Abstract: "Memory isolation is critical for system reliability, security, and safety. Unfortunately, read disturbance can break memory isolation in modern DRAM chips. For example, RowHammer is a well-studied read-disturb phenomenon where repeatedly opening and clo... » read more

Week In Review: Design, Low Power


DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing. Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler EDA and IP remain strong, approaching $4 billion in Q1, according to ... » read more

Antenna For Nanoscale Light Source By Placing The TMD Outside The Tunnelling Pathway


A technical paper titled "Exciton-assisted electron tunnelling in van der Waals heterostructures" was published by researchers at ETH Zürich, The Barcelona Institute of Science and Technology, Swiss Federal Laboratories for Materials Science and Technology, National Institute for Materials Science, University of Basel, and Institució Catalana de Recerca i Estudis Avançats (ICREA). Abstract:... » read more

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