Week In Review: Design, Low Power

By Susan Rambo - 14 Jul, 2023 - Comments: 0

DAC and SEMICON WEST rebounded this year, focusing on everything from security to chiplets and smart manufacturing. Panel at DAC conference: Left to right, ARM’s Brian Fuller (moderator), Joe Costello (Metrics, Kwikbit, Arrikto, Acromove), and Wally Rhines (Cornami). Source: Semiconductor Engineering/Ann Mutschler EDA and IP remain strong, approaching $4 billion in Q1, according to ... » read more

Antenna For Nanoscale Light Source By Placing The TMD Outside The Tunnelling Pathway

By Technical Paper Link - 13 Jul, 2023 - Comments: 0

A technical paper titled "Exciton-assisted electron tunnelling in van der Waals heterostructures" was published by researchers at ETH Zürich, The Barcelona Institute of Science and Technology, Swiss Federal Laboratories for Materials Science and Technology, National Institute for Materials Science, University of Basel, and Institució Catalana de Recerca i Estudis Avançats (ICREA). Abstract:... » read more

Chip Industry’s Technical Paper Roundup: June 27

By Liz Allan - 27 Jun, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=113 /] » read more

A Field-Free Switching Solution For SOT Magnetic Tunnel Junction Devices

By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Field-Free Spin-Orbit Torque Driven Switching of Perpendicular Magnetic Tunnel Junction through Bending Current” was published by researchers at KU Leuven, ETH Zurich, and IMEC. Abstract: "Current-induced spin-orbit torques (SOTs) enable fast and efficient manipulation of the magnetic state of magnetic tunnel junctions (MTJs), making them attractive for memory, i... » read more

Chip Industry’s Technical Paper Roundup: June 20

By Liz Allan - 20 Jun, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=112 /] » read more

Object Detection CNN Suitable For Edge Processors With Limited Memory

By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers” was published by researchers at ETH Zurich. Abstract: "This paper introduces a highly flexible, quantized, memory-efficient, and ultra-lightweight object detection network, called TinyissimoYOLO. It aims to enable object detection on microcontrol... » read more

Chip Industry’s Technical Paper Roundup: June 13

By Liz Allan - 13 Jun, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=109 /] Further Reading Technical Paper Home » read more

Advantages, Disadvantages, And Use Cases Of FPGAs

By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “Data Processing with FPGAs on Modern Architectures” was published by researchers at ETH Zürich. Abstract: "Trends in hardware, the prevalence of the cloud, and the rise of highly demanding applications have ushered an era of specialization that is quickly changing the way data is processed at scale. These changes are likely to continue and accelerate in the next... » read more

Chip Industry’s Technical Paper Roundup: June 5

By Linda Christensen - 05 Jun, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=105 /] More Reading Technical Paper Library home » read more

Rowhammer Vulnerability Of A HBM2 DRAM Chip

By Technical Paper Link - 01 Jun, 2023 - Comments: 0

A new technical paper titled "An Experimental Analysis of RowHammer in HBM2 DRAM Chips" was published by researchers at ETH Zurich and American University of Beirut. Abstract: "RowHammer (RH) is a significant and worsening security, safety, and reliability issue of modern DRAM chips that can be exploited to break memory isolation. Therefore, it is important to understand real DRAM chips' ... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

tag: ETH Zurich