Chip Industry’s Technical Paper Roundup: November 6

MIT-CSAIL’s HW security modules; HW acceleration for high performance edge; 2D materials for next-gen FETs; wireless control for SiC power MOSFETs; 3D NAND improvements; CPU fuzzing; van der Waals nanophotonics; shallow clock tree pre-estimation.


New technical papers added to Semiconductor Engineering’s library this week.

Technical Paper Research Organizations
The K2 Architecture for Trustworthy Hardware Security Modules MIT CSAIL and New York University
Fault-Tolerant Hardware Acceleration for High-Performance Edge-Computing Nodes University of Rome
Field-Effect Transistors based on 2-D Materials: a Modeling Perspective ETH Zurich
Wireless Control of Active Gate Drivers for Silicon Carbide power MOSFETs Norwegian University of Science and Technology (NTNU)
3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer Myongji University, Soongsil University, and Seoul National University
Cascade: CPU Fuzzing via Intricate Program Generation ETH Zurich
Deeply subwavelength integrated excitonic van der Waals nanophotonics University of California Los Angeles, University of Washington Seattle, and Auburn University
Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs Kyungpook National University

More Reading
Technical Paper Library home

Leave a Reply

(Note: This name will be displayed publicly)