Chip Industry’s Technical Paper Roundup: November 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=162 /] More Reading Technical Paper Library home » read more

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)


A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Chip Industry’s Technical Paper Roundup: Nov. 1


New technical papers added to Semiconductor Engineering’s library this week. [table id=61 /] » read more

In-NAND Flash Processing Technique for Improved Performance, Energy Efficiency & Reliability of Bulk Bitwise Operations


A new technical paper titled "Flash-Cosmos: In-Flash Bulk Bitwise Operations Using Inherent Computation Capability of NAND Flash Memory" was published by researchers at ETH Zurich, POSTECH, LIRMM/Univ. Montpellier/CNRS and Kyungpook National University. Find the technical paper here (published September 2022) and related YouTube lecture here. "We propose Flash-Cosmos (Flash Computation wi... » read more