tag: EUV

Week In Review: Manufacturing, Test
By Mark LaPedus - 21 Feb, 2020 - Comments: 0

Fab tools The United States is mulling over new trade export restrictions for U.S. fab equipment to China, according to a report from The Wall Street Journal. “Recent press reports suggest the U.S. Department of Commerce is exploring additional measures to limit Huawei's access to U.S. semiconductor capital equipment (SPE) by requiring chip manufacturing plants globally to procure license... » read more

The Risk Of Two Supply Chains
By Ed Sperling - 20 Feb, 2020 - Comments: 0

Ever since the Trump administration weaponized trade restrictions against individual companies — first ZTE, then Huawei — China has begun developing a second supply chain for electronics. Inside of China, this is viewed as a necessary step for survival. In April 2018, the U.S. government banned ZTE from sourcing U.S. components for seven years, nearly putting that company out of business... » read more

EDA In The Cloud
By Ed Sperling - 18 Feb, 2020 - Comments: 0

Michael White, director of product marketing for Calibre physical verification at Mentor, a Siemens Business, looks at the growing compute requirements at 7, 5 and 3nm, why the cloud looks increasingly attractive from a security and capacity standpoint, and how the cloud as well as new lithography will affect the cost and complexity of developing new chips. » read more

Extreme Quality Semiconductor Manufacturing
By Ben Tsai - 11 Feb, 2020 - Comments: 0

By Ben Tsai and Cathy Perry Sullivan Across the full range of semiconductor device types and design nodes, there is a drive to produce chips with significantly higher quality. Automotive, IoT and other industrial applications require chips that achieve very high reliability over a long period of time, and some of these chips must maintain reliable performance while operating in an environmen... » read more

AI And Big Data Set To Reinvent Semiconductor Industry
By Regina Freed - 23 Jan, 2020 - Comments: 0

The recent IEEE International Electron Devices Meeting (IEDM) reaffirmed that the semiconductor industry is in a period of reinvention as we grapple with the challenges and opportunities promised by the Internet of Things (IoT), Big Data and AI. That such change is underway was made evident by a panel I was honored to moderate titled, “The Future of Logic: EUV is Here, Now What?” Joining... » read more

Finding Defects In EUV Masks
By Mark LaPedus - 23 Jan, 2020 - Comments: 0

Extreme ultraviolet (EUV) lithography is finally in production at advanced nodes, but there are still several challenges with the technology, such as EUV mask defects. Defects are unwanted deviations in chips, which can impact yield and performance. They can crop up during the chip manufacturing process, including the production of a mask or photomask, sometimes called a reticle. Fortunately... » read more

Where Technology Breakthroughs Are Needed
By Mark LaPedus - 23 Dec, 2019 - Comments: 2

After years of delays, extreme ultraviolet (EUV) lithography is finally in production at the 7nm logic node with 5nm in the works. EUV, a next-generation lithography technology, certainly will help chipmakers migrate to the next nodes. But EUV doesn’t solve every problem. Nor does it address all challenges in the semiconductor industry. Not by a long shot. To be sure, the industry needs... » read more

Multi-Patterning EUV Vs. High-NA EUV
By Mark LaPedus - 04 Dec, 2019 - Comments: 4

Foundries are finally in production with EUV lithography at 7nm, but chip customers must now decide whether to implement their next designs using EUV-based multiple patterning at 5nm/3nm or wait for a new single-patterning EUV system at 3nm and beyond. This scenario revolves around ASML’s current extreme ultraviolet (EUV) lithography tool (NXE:3400C) versus a completely new EUV system with... » read more

Making And Protecting Advanced Masks
By Mark LaPedus - 27 Nov, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask trends with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Thomas Scheruebl, director of strategic business development and product strategy at Zeiss; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What fol... » read more

DRAM Scaling Challenges Grow
By Mark LaPedus - 21 Nov, 2019 - Comments: 5

DRAM makers are pushing into the next phase of scaling, but they are facing several challenges as the memory technology approaches its physical limit. DRAM is used for main memory in systems, and today’s most advanced devices are based on roughly 18nm to 15nm processes. The physical limit for DRAM is somewhere around 10nm. There are efforts in R&D to extend the technology, and ultimate... » read more

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