tag: EUV

Gaps Remain For EUV Masks
By Mark LaPedus - 02 Oct, 2015 - Comments: 4

Extreme ultraviolet (EUV) lithography is once again at a critical juncture. The oft-delayed technology is now being targeted for 7nm. But there are still a number of technologies that must come together before EUV is inserted into mass production at that node. First, the EUV source must generate more power. Second, tool uptime must improve. Third, the industry needs better EUV resists. A... » read more

Resist Sensitivity, Source Power, And EUV Throughput
By Katherine Derbyshire - 30 Sep, 2015 - Comments: 0

In a recent article, I quoted 15 mJ/cm2 as the target sensitivity for EUV photoresists, and discussed the throughput that could be achieved at various source power levels. However, as a commenter on that article pointed out, reaching the 15 mJ/cm² target while also meeting line roughness requirements is itself a challenging problem. Because of the high energy of EUV photons, a highly sensitive... » read more

Survey: Mask Complexity To Increase
By Mark LaPedus - 29 Sep, 2015 - Comments: 1

The eBeam Initiative today released its annual members’ perceptions survey, a set of results that reveals some new and surprising data about EUV, multi-beam and photomask technology. As part of the results in the new survey, there is a growing level of optimism for the implementation of extreme ultraviolet (EUV) lithography in high-volume manufacturing, as compared to last year’s results... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge
By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

EUV: Cost Killer Or Savior?
By Katherine Derbyshire - 17 Sep, 2015 - Comments: 4

Moore’s Law, the economic foundation of the semiconductor industry, states that transistor density doubles in each technology generation, at constant cost. As IMEC’s Arindam Mallik explained, however, the transition to a new technology node is not a single event, but a process. Typically, when the new technology is first introduced, it brings a 20% to 25% wafer cost increase. Process opt... » read more

New Options For Power
By Ed Sperling - 10 Sep, 2015 - Comments: 0

Chipmakers have been talking for years about the next big breakthrough in battery technology, low-power architectures and energy harvesting. So far, none of them has made their job any easier. Batteries empty out too quickly, and the technology for improving the amount of energy that can be stored don't improve fast enough—or safely enough when they do show big improvements—to make a big... » read more

Manufacturing Bits: Sept. 1
By Mark LaPedus - 01 Sep, 2015 - Comments: 0

Free-electron laser EUV consortium Extreme ultraviolet (EUV) lithography is delayed. Chipmakers hope to insert EUV at the 7nm node, but that’s not a given. As before, the big problem is the EUV light source. So far, the source can’t generate enough power to enable the required throughput for EUV in high-volume production. ASML’s current EUV source is operating at 80 Watts, up from 10 ... » read more

Interconnect Challenges Grow
By Mark LaPedus - 20 Aug, 2015 - Comments: 1

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate. So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more

What Works After 7nm?
By Mark LaPedus - 20 Aug, 2015 - Comments: 3

An Steegen, senior vice president of process technology at [getentity id="22217" e_name="Imec"], the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm. SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right? Steegen:... » read more

Pathfinding Beyond 10nm
By Paula Doe - 10 Aug, 2015 - Comments: 0

After higher aspect-ratio finFETs and higher mobility SiGe and III-V materials, the industry will move to lateral nanowires and then to vertical nanowire transistors, and to new tunnel junction FETs or spin wave architectures ─ or to various combinations of these technologies for different applications, reported An Steegan, Imec senior vice president of process technology, during SEMICON West... » read more

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