How To Extend Litho Scaling

By Ann Mutschler - 19 Feb, 2015 - Comments: 0

IC mask [getkc id="80" comment="lithography"] today is sophisticated and complex. It's also a work in progress with a lot of unknowns as the industry struggles to increase productivity while reducing risk. The bulk of the work currently is focused on trying to figure out what would be a practical scheme for patterning lithography that could be used at 10nm and 7nm, said Gandharv Bhatara, Ca... » read more

One-On-One: Dave Hemker

By Mark LaPedus - 19 Feb, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Dave Hemker, senior vice president and chief technology officer at [getentity id="22820" comment="LAM Research"]. SE: On the technology front, the IC industry is undergoing some new and dramatic changes. What are some of those changes? Hemker: We focus on what we call the inflections.... » read more

First Look: 10nm

By Ed Sperling - 29 Jan, 2015 - Comments: 6

As the semiconductor industry begins grappling with mass production at 14/16nm process nodes, work is already underway at 10nm. Tools are qualified, IP is characterized, and the first test chips are being produced. It's still too early for production, of course—perhaps three years too early—but there is enough information being collected to draw at least some impressions about just how toug... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 23 Jan, 2015 - Comments: 0

The profile of a "tech geek" is typically a male. The label itself has transitioned from a negative to a positive connotation, according to new data from Crucial.com. In fact, almost half of women (45%) identified tech entrepreneurs as the most desirable potential spouse, compared to only 5% of women who would prefer a football player for a spouse. More than one in three women want a significan... » read more

One-On-One: Aaron Thean

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss process technology, transistor trends and other topics with Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. SE: Chipmakers are ramping up the 16nm/14nm logic node, with 10nm and 7nm in R&D. What’s the current timeline for 10nm and 7nm? Thean: 10nm is on its way. We will see r... » read more

Fab Tool R&D And Ramen Noodles

By Mark LaPedus - 22 Jan, 2015 - Comments: 0

The semiconductor equipment and materials industry has always been a tough business. Over the years, vendors have been under pressure to develop new technologies for a shrinking but demanding customer base. And as a result, many vendors could not keep up, or elected to exit the business, causing a massive shakeout in the industry. It isn’t getting any easier, though. Today, tool and... » read more

Industry Scorecard For 2014

By Brian Bailey - 22 Dec, 2014 - Comments: 0

At the end of last year, Semiconductor Engineering asked the industry about the developments they expected to see in 2014. If you care to refresh your memory, they were categorized under markets, semiconductors and development tools. Now it is time to look back and see how accurate those predictions were and where they fell short. Part one addressed the market and semiconductor areas and in thi... » read more

Unraveling The Mysteries At IEDM

By Mark LaPedus - 19 Dec, 2014 - Comments: 0

In some respects, the 2014 IEEE International Electron Devices Meeting (IEDM) was no different than past events. The event, held this week in San Francisco, included the usual and dizzying array of tutorials, sessions, papers and panels. On the leading-edge CMOS front, for example, the topics included [getkc id="82" kc_name="2.5D"]/[getkc id="42" kc_name="3D IC"] chips, III-V materials, [getkc ... » read more

And the Winner is…

By Brian Bailey - 18 Dec, 2014 - Comments: 0

Semiconductor Engineering now has its first full year under its belt, and I have to say it has been an incredible year. Not only did we exceed a million page views in our first year, but we also got started on the Knowledge Center, an endeavor the likes of which has never been attempted in our industry. It is still very young and has a lot of growing up to do, but it is a wonderful start. We wo... » read more

Tech Talk: Inverse Lithography

By Ed Sperling - 11 Dec, 2014 - Comments: 0

D2S’ Leo Pang talks with Semiconductor Engineering about lithography, inverse lithography, photomasks, where the problems are, and what needs to be done to move forward. [youtube vid=mn8JWaP8Z68] » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?