tag: EUV

Breaking The 2nm Barrier
By Mark LaPedus - 18 Feb, 2021 - Comments: 4

Chipmakers continue to make advancements with transistor technologies at the latest process nodes, but the interconnects within these structures are struggling to keep pace. The chip industry is working on several technologies to solve the interconnect bottleneck, but many of those solutions are still in R&D and may not appear for some time — possibly not until 2nm, which is expected t... » read more

Imec’s Plan For Continued Scaling
By Paul McLellan - 14 Jan, 2021 - Comments: 0

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than Moore (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world sinc... » read more

AI And High-NA EUV At 3/2/1nm
By Mark LaPedus - 16 Dec, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

EUV Challenges And Unknowns At 3nm and Below
By Mark LaPedus - 19 Nov, 2020 - Comments: 1

The chip industry is preparing for the next phase of extreme ultraviolet (EUV) lithography at 3nm and beyond, but the challenges and unknowns continue to pile up. In R&D, vendors are working on an assortment of new EUV technologies, such as scanners, resists, and masks. These will be necessary to reach future process nodes, but they are more complex and expensive than the current EUV pro... » read more

What’s Next In AI, Chips And Masks
By Mark LaPedus - 19 Nov, 2020 - Comments: 0

Aki Fujimura, chief executive of D2S, sat down with Semiconductor Engineering to talk about AI and Moore’s Law, lithography, and photomask technologies. What follows are excerpts of that conversation. SE: In the eBeam Initiative’s recent Luminary Survey, the participants had some interesting observations about the outlook for the photomask market. What were those observations? Fujimur... » read more

Survey: eBeam Initiative Luminaries (formerly Perceptions) Survey Results
By eBeam Initiative - 18 Nov, 2020 - Comments: 0

Survey of 77 industry luminaries across 42 different companies in July 2020 says net neutral COVID-19 business impact by 2021, with 24% positive vs 20% negative predictions. Click here to view the survey results. » read more

Challenges Linger For EUV
By Mark LaPedus - 11 Nov, 2020 - Comments: 2

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. To vie... » read more

Manufacturing Bits: Nov. 9
By Mark LaPedus - 09 Nov, 2020 - Comments: 0

Open-source EUV resist metrology Paul Scherrer Institute (PSI) has developed an open-source software technology for scanning electron microscopy (SEM) applications. The technology is targeted for EUV resist metrology. The technology, called SMILE (SEM-Measured Image Lines Estimator), is an open source software technology, which characterizes line and space patterns in a SEM. SMILE is used t... » read more

Si Hardmask (Si-HM), EUV And Zero Defects
By Hao Lee - 26 Oct, 2020 - Comments: 0

The multilayer system used in lithography consists of a planarizing carbon layer beneath a hardmask etch-transferring layer and capped with a standard photoresist coating. In the past, Brewer Science has discussed in-depth how the multilayer system helped to extend ArF (193 nm) immersion lithography to be able to print and transfer ever-shrinking features, ensuring enough process window especia... » read more

Mask/Lithography Issues For Mature Nodes
By Mark LaPedus - 22 Oct, 2020 - Comments: 0

Semiconductor Engineering sat down to discuss lithography and photomask issues with Bryan Kasprowicz, director of technology and strategy and a distinguished member of the technical staff at Photronics; Harry Levinson, principal at HJL Lithography; Noriaki Nakayamada, senior technologist at NuFlare; and Aki Fujimura, chief executive of D2S. What follows are excerpts of that conversation. ... » read more

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