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EUV Pellicles Finally Ready

Yield rises with mask protection; multiple sources will likely reduce costs.

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After a period of delays, EUV pellicles are emerging and becoming a requirement in high-volume production of critical chips.

At the same time, the pellicle landscape for extreme ultraviolet (EUV) lithography is changing. ASML, the sole supplier of EUV pellicles, is transferring the assembly and distribution of these products to Mitsui. Others are also developing pellicles for EUV, a next-generation lithography technology that patterns tiny features on chips using 13.5nm wavelengths.

A key part of the IC supply chain, a pellicle is a thin transparent membrane that protects an expensive photomask during the chip production flow. In a generic flow for traditional optical lithography, an IC maker designs a chip, which is then translated into a file format. Then, in a photomask facility, that file is transformed into a mask. The photomask is a master template for an IC design.

A pellicle is then mounted on the photomask, preventing particles from falling on the mask during the production process. At that point, the mask is shipped to the fab. In the fab, a wafer as well as the mask with a pellicle on top are placed in a lithography scanner. The scanner then projects light through the mask onto the wafer, creating patterns on the wafer.

Without a pellicle, the results can be catastrophic. If a particle lands on a mask, the scanner could print repeating defects on the wafer, which negatively impacts yield. It’s important to protect the photomask for another reason. Today, the average price for a leading-edge optical mask is around $100,000, while an EUV mask is approximately $300,000, according to analysts.

EUV and optical lithography are different technologies, but the flow is similar. When EUV was first inserted into production at 7nm in 2018, EUV pellicles weren’t ready. EUV pellicles use different and more complex materials than pellicles for optical lithography.

Still, some chipmakers put EUV into production without pellicles, and they manufactured advanced chips with mixed results. At the latest nodes, though, the processes are becoming more complex, and unwanted defects are smaller and harder to find in chips. EUV processes are also becoming more complex, and potential defects and yield losses are at play.

Fortunately, EUV pellicles are emerging to help some but not all issues. So after sitting on the sidelines, EUV pellicles are fast becoming a requirement and being adopted for select chips. “Trying to do EUV without pellicles is painful. It requires much more metrology, and there is still potential for yield loss,” said Harry Levinson, principal at HJL Lithography. “With higher power sources and higher transmission pellicles, it could well be that people are deciding to use pellicles.”

But developing EUV pellicles has been difficult, and the industry is still struggling to meet the desired specs. Finally, some options are emerging, including:

  • ASML’s EUV pellicles are closing in on the desired specs. ASML is also transferring its EUV pellicle business to Mitsui.
  • Imec disclosed new results with the development of EUV pellicles based on carbon nanotubes.
  • Graphene Square and FST, as well as several universities, are developing EUV pellicles in R&D.


Fig. 1: ASML’s EUV pellicle Source: ASML

Moving from optical to EUV
For years, chipmakers used optical-based lithography scanners, coupled with optical-oriented pellicles, to pattern the features in chips. Measuring 6 x 6 inches and ¼-inch thick, an optical photomask consists of an opaque layer of chrome on a glass substrate.

“The photomask, also called a reticle or just a mask, contains what you want to print on the wafer,” explained Chris Mack, CTO of Fractilia, in a video presentation. “It has opaque regions where we want to block the light, and is transparent where we want the light to go through.”

Each mask contains the patterns of one or more dies, depending the size of the chip. “We have lots of lithography steps that build up all of the patterns of transistors, isolation, metallization runs and contact holes. They are used to make up these complicated integrated circuits,” Mack said. “We need lots of photomasks — at least one for every lithography layer. 180nm node devices need about 25 masks, 32nm node devices need about 50 masks, and 16nm node devices need about 75 masks.”

On top of that, the features on the mask are smaller and more complex at each node. Optical masks consist of tiny features that resemble rectangular shapes.

At 3nm and beyond, chipmakers hope to develop curvilinear shapes on the mask. “The reason you want curvilinear shapes on the mask is because wafer quality improves substantially. That is even more important for EUV than in 193nm immersion lithography,” said Aki Fujimura, chief executive of D2S.

Mask making is also more difficult at each node. To make a mask for optical lithography, the first step is to create a mask blank. Made by a mask blank vendor, the blank serves as the base structure of a mask.

Once the blank is made, it is shipped to the photomask vendor, where the actual mask is produced. To make a mask, the blank is patterned, etched, repaired and inspected.

Because the mask is so critical and expensive, it’s important to protect it. That’s where pellicles fit in. At the end of the flow, a polymer-based pellicle is mounted on the mask. It acts like a dust cover, protecting particles from landing on the mask. “For DUV and longer wavelength lithography, pellicles are ubiquitous, inexpensive and made of fluoropolymers that have more than 99% transmittance at the exposure wavelength,” said Emily Gallagher, a principal member of technical staff at Imec.

Optical-based lithography and photomask processes are complex but well-understood. All of that changed when chipmakers migrated to EUV lithography at 7nm in 2018.

Using multiple patterning, chipmakers extended 193nm lithography down to 7nm. But at today’s 5nm process node, it’s too complex to use these techniques. That’s where EUV fits in. EUV simplifies the process and enables chipmakers to pattern the most difficult features at 7nm and beyond. “A single EUV exposure replaces three or more optical exposures. EUV patterns have show tighter electrical distributions. A single EUV exposure can improve EPE by 90%,” said Kazuya Okubo, vice president of integrated solution planning at TEL, during a presentation at SPIE Advanced Lithography.

But EUV also took longer than expected to bring into production amid delays with the technology. Today, though, chipmakers are in production using ASML’s EUV scanners. Incorporating a 0.33 numerical aperture (NA) lens with 13nm resolutions, the system has a throughput from 135 to 145 wafers per hour.

Samsung and TSMC are using ASML’s EUV scanners for chip production at 7nm and 5nm. Intel plans to insert ASML’s EUV tools at advanced nodes. Additionally, Samsung and SK Hynix will use EUV for DRAM production.

Demand is strong for EUV. “We estimate ASML shipped 32 EUV units, while recognized revenue on 31 units in calendar year 2020,” said Krish Sankar, an analyst at Cowen. “This year, we forecast 40 units for ASML’s EUV. ASML is supply constrained on EUV units for 2021.”

Besides procuring enough EUV tools, chipmakers face other challenges. “Essentially, EUV 0.33 NA came to market much later than hoped. By that time, multiple patterning had already been implemented in immersion lithography. We were already, in many cases, past the limit of what a 0.33 NA tool would be able to print in a single pass,” said Richard Wise, vice president at Lam Research. “So the industry is already employing EUV double patterning at some levels. There are challenges with EUV double patterning, and they are very analogous to what was seen in immersion double patterning. Double patterning means more mask levels, which can drive additional cost. EUV masks are, in general, more costly than the previous generations of lithography. Multiple patterning in EUV is enabling, but does drive additional costs for customers.”

In response, ASML in R&D is working on a next-generation technology called high-numerical aperture (high-NA) EUV. Targeted for 3nm/2nm in 2022, that system features a 0.55 NA lens capable of 8nm resolutions.

High-NA EUV promises to bring the industry back to single patterning. “The current state of EUV is solid and is here to stay,” said Doug Guerrero, senior technologist at Brewer Science. “High-NA is still in its infancy. It might be two years out before a tool is even available. Maybe another five after that before we see a real tool.”

EUV mask/pellicle challenges
Like optical lithography, EUV also requires a photomask. Unlike optical masks, which are transmissive, EUV masks are reflective. EUV masks are different in other ways. An EUV mask consists of 40 to 50 thin alternating layers of silicon and molybdenum on a substrate. This results in a multi-layer stack that is 250nm to 350nm thick. On the stack, there is a ruthenium-based capping layer, followed by an absorber based on a tantalum material.


Figure 2: Cross-section of an EUV mask. In EUV, light hits the mask at an angle of 6°. Source: Luong, V., Philipsen, V., Hendrickx, E., Opsomer, K., Detavernier, C., Laubis, C., Scholze, F., Heyns, M., “Ni-Al alloys as alternative EUV mask absorber,” Appl. Sci. (8), 521 (2018). (Imec, KU Leuven, Ghent University, PTB)

EUV masks are manufactured like optical masks. An EUV mask blank is developed, and then patterned, etched, repaired and inspected.


Fig. 3: EUV mask fabrication steps. Source: Sematech

In the early stages of EUV, though, the industry insisted that EUV masks didn’t require a pellicle. The industry believed that EUV scanners would remain 100% clean during the process flow. They assumed EUV masks would remain particle free.

But chipmakers soon realized that they couldn’t guarantee that the EUV scanner could remain 100% clean during the flow. Suddenly, chipmakers wanted EUV pellicles, but development of these components started relatively late. This, in turn, caused some delays with EUV pellicles.

Basically, optical and EUV pellicles use different materials. For example, ASML’s EUV pellicle is based on polysilicon that is 50nm thick.

EUV pellicles also must be robust. In EUV, the light is generated and bounces off several mirrors. When EUV light hits the pellicle situated on the mask, the temperature of the membrane will heat up anywhere from 600 to 1,000º Celsius.

Then, because EUV uses reflective masks, EUV energy goes through the pellicle twice, once on the way to the mask and once on the way back from the wafer. In theory, the pellicle will dissipate the heat. But at those temperatures, pellicles possibly could deteriorate.

For high-volume manufacturing, EUV pellicles must meet various specs in the following areas —transmission, power capabilities, defects and others. Inspection is another issue.

“EUV pellicles need far more than 90% of transmittance to support the defectivity and productivity of EUV lithography,” said Naoya Hayashi, a research fellow at DNP. “The lifetime of a pellicle is also an issue.”

That’s been a major stumbling block. Until recently, ASML’s EUV pellicles had a transmission rate below 90%. EUV works at these rates, but it slows down the process and reduces scanner throughputs from 11% to 20%, according to analysts.

The challenge is to find the right pellicle material that can dissipate the heat and maintain the desired transmission rates. Cost is also key.

“Most materials absorb very strongly at the more energetic 13.5nm EUV wavelength and, even when the most EUV-transparent materials are selected, the membranes must be extremely thin to approach 90% transmittance,” Imec’s Gallagher said. “Such thin membranes are not usually capable of maintaining sufficient strength to be free-standing at the required dimensions. Additionally, the EUV scanner environment is not compatible with many materials and will subject the pellicle to pump-vent cycles.”

If that’s not enough to consider, chipmakers also need to develop a strategy around pellicles. Generally, they have three options:

  • Wait for EUV pellicles to meet the desired spec before using them in production.
  • Move into EUV production without pellicles.
  • Use EUV pellicles for some but not all chips.

Of course, not all devices require EUV. Many chips are based on mature nodes and are patterned using traditional optical lithography.

Meanwhile, at the high end, Intel has opted to wait for EUV pellicles, because it tends to develop large chips using single die reticles. In a worst-case scenario, the yield hit from just one particle adder in a single-die reticle is 100%, which translates to zero yields, according to analysts. In the same scenario, you would obtain 50% less yield in a two-die reticle, analyst said.

So pellicles are critical for large die sizes, but less essential for smaller chips. In the same scenario, you would obtain only 4% less yield for a 25-die reticle, analysts said.

Nonetheless, Samsung and TSMC initially moved into EUV production without pellicles, simply because these components weren’t ready. The results are mixed. Using EUV, chipmakers have produced a multitude of chips, although the yields have ranged anywhere from satisfactory to poor, according to multiple sources in the equipment industry. This depends on the chip size, design and vendor, sources said.

On top of that, a chipmaker must clean the EUV mask often to get rid of the particles on the structure. Then, a vendor must inspect the mask often to ensure there are no defects on the structure. All of these steps are time-consuming and costly.

In response, TSMC developed a new dry-clean EUV mask cleaning process to reduce time and costs. “Instead of using traditional wet clean processes with ultrapure water and chemicals, fall-on particles are rapidly removed by a dry clean technique. With persistent tests and optimization, the fall-on particle reduction rate achieved more than 99% in 2020,” according to three TSMC researchers, James Chu, Ivence Hu and Jenna Chang, in a recent blog.

Recently, though, EUV pellicles from ASML are moving toward the desired specs. Initially, chipmakers were reluctant to use them due to cost, throughput and other factors — or they want to use pellicles, but it takes time to integrate them.

Not surprisingly, chipmakers are taking yield hits on some chips, namely the larger dies, according to sources in the equipment business. On the other hand, DRAMs may not require EUV pellicles. DRAM vendors will add more die area devoted to redundancy to deal with particles ending up on the EUV mask. Regardless, in some cases, customers are pushing back, demanding that their foundry partners use EUV pellicles for select chips, sources added.

EUV pellicle supply chain
For those who need pellicles, the choices are limited. In the mid-2010s, ASML, IBM, Samsung and others were developing EUV pellicles. Over time, ASML emerged as the sole supplier of EUV pellicles in the industry.

In 2016, ASML developed its first polysilicon-based EUV pellicles. At the time, ASML’s pellicle demonstrated 78% transmissions on a simulated 175-watt source. By 2020, ASML improved the transmission performance of its EUV pellicle to greater than 88%. The current pellicle has a transmission non-uniformity spec of 0.4% with less than 0.04% reflectivity.

ASML’s new prototype EUV pellicles are said to have 90.6% transmission rates with 0.2% non-uniformities with less than 0.005% reflectivity. The power capability is 400 watts.

Low transmission non-uniformities and reflectivity are important specs. “EUVT (transmission) non-uniformity impacts the dose uniformity within the image field, resulting in CDU in the exposed fields,” said Raymond Lafarre, a system architect at ASML, in a recent presentation. “The EUVR (reflectivity) of the pellicles should be low to avoid larger dose in the image field corners on the wafer.”

Making EUV pellicles is complex. The development of the pellicle membranes is done at Teledyne, in cooperation with ASML. To make the pellicle itself, ASML developed its own EUV pellicle assembly and mounting tools.

To characterize EUV pellicles, RI Research Instruments developed a pellicle reflection/transmission measurement system. Another vendor, FMI, developed a tool that measures the deflection of the pellicle at low delta pressures.

Long-term, however, chipmakers want to procure EUV pellicles from another vendor. They want ASML to focus on the development of EUV scanners. So ASML is transferring the EUV pellicle production and distribution functions to Mitsui.

The pellicle production tools have been installed in Mitsui, which this year will ramp up EUV pellicles based on ASML’s technology. Mitsui is no stranger to pellicles, and already produces optical pellicles. ASML will continue to do R&D for future pellicles.

The supply chain isn’t the only issue with ASML-developed pellicles. In the mask shop and fab, vendors want to inspect the photomask for defects. There are different tool types to inspect EUV masks, such as actinic, e-beam and optical.

Vendors will use each one in EUV mask inspection. The pellicle plays a role here. For example, optical inspection, the dominant tool in the mask shop, can’t inspect EUV masks with the pellicle on top. Unfortunately, the polysilicon-based material is opaque at 193nm wavelengths.

So ASML has developed a retractable pellicle. In operation, the EUV pellicle is automatically raised and a tool inspects the mask. Once that task is completed, the pellicle is automatically lowered and re-attached to the EUV mask.

This is a headache. Fortunately, Lasertec has developed an actinic patterned mask inspection (APMI) system. Because APMI uses the same 13.5nm wavelength as EUV, this system can inspect an EUV mask with a pellicle on top.

Long-term, meanwhile, EUV pellicles face other challenges. “Few materials have the potential of high EUV transmission beyond 90% and even fewer materials are at the same time compatible with EUV powers beyond 600W. In addition, the pellicle needs to be strong to be suspended over a large area of the mask (~110mm x 140mm),” said Joost Bekaert, a researcher from Imec, in a recent paper. Others from Imec and ASML contributed to the work.

For some time, Imec has been developing EUV pellicles based on carbon nanotubes. Based on carbon materials, carbon nanotubes have better electrical and thermal properties than silicon, and are 100 times stronger than steel at one-sixth the weight.


Fig. 4: Imec’s carbon nanotube pellicle. Source: Imec

A carbon nanotube is a tiny rolled-up cylindrical sheet of graphene that comes in various versions. Single-walled carbon nanotubes consists of one rolled-up sheet of graphene, while multi-walled carbon nanotubes incorporate several sheets.

Imec’s nanotube pellicles aren’t quite ready for mass production, but the R&D organization has made some impressive progress. Imec’s pellicles have demonstrated 97.7% transmissions on ASML’s EUV scanners.

“We have described different types of CNT materials, but the real point is that the CNT membrane is tunable with variables like the number of walls in each CNT tube, the density of tubes and the degree of bundling,” Imec’s Gallagher said. “For the purposes of this paper, we talked about walls — single-, double- and multi-walled CNTs. They have different strengths and weaknesses, but multiple walls demonstrated more stable behavior when exposed to EUV scanner-like conditions.”

Both single- and multi-wall pellicles are promising. “Both types performed well showing minimal imaging differences over the no-pellicle reference for CD uniformity, LWR and flare. The minor increase in dose was anticipated based on measured EUV absorption that ranged from 95.3% to 97.7% on these pellicles,” Gallagher said.

Another advantage with nanotube pellicles is inspection. “The CNTs are transparent through all the inspection wavelengths, enabling both DUV and actinic inspection,” Gallagher said.

Conclusion
Clearly, EUV pellicles are important to continued scaling. Thankfully, the ASML-developed pellicle has arrived and the supply chain is solid.

Still, chipmakers would like to have more and different EUV pellicle options, especially as the challenges increase in EUV.

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EUV Challenges And Unknowns At 3nm and Below



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