Manufacturing Bits: March 8

Two-beam EUV lithography; EUV SADP; dry resists.


Two-beam EUV lithography
At the recent SPIE Advanced Lithography conference, Nikon gave a presentation on a two-beam extreme ultraviolet (EUV) lithography technology.

Still in the conceptual phase, Nikon’s so-called EUV Projection Optical Wafer Exposure Ruling Machine, or EUV Power Machine, is designed for the 1nm node or so. The proposed system has a minimum resolution of 10nm for lines and spaces in single patterning applications.

If it ever gets built and appears in the market, Nikon’s system appears to be a competitor to ASML’s high-numerical aperture EUV technology. Still in R&D, ASML is developing a new high-NA EUV system that features a radical 0.55 NA lens capable of 8nm resolutions. The 0.55 NA tool is targeted for the 3nm node in 2023, but it will likely appear at a later node, such as 2nm. The mammoth-size tool is extremely complex and expensive.

Beyond 3nm, meanwhile, chipmakers have several options to pattern the most difficult features in chips. Today’s 0.33 NA EUV with double patterning is one option. High-NA EUV is another option.

Nikon is also throwing its hat in the ring with the EUV Power Machine, but it’s unclear if the technology will ever get off the ground. It requires massive funding and backing from industry partners.

Nonetheless, Nikon’s system is different than ASML’s EUV tools. “This is a two-beam imaging system. That’s not an interference system because it has a direct object to the image relationship,” said Donis Flagello, president and CEO of Nikon Research Corp. of America, in a presentation at SPIE.

On paper, the system resembles a traditional EUV system. Nikon’s 0.4 NA projection optics has a compact symmetric design with two reflections in the mirrors.

“There’s no reticle scanning, only wafer scanning in 1D. This also helps with the cost. It will scan the entire 300mm wafer with stitching, and it won’t be stepping. To reduce the optic size, we limit the pitches. So we limit the pitches between a 20 and 30 nanometer pitch. This gives the system a minimum resolution of 10nm line spaces,” Flagello said.

The proposed system has a throughput of much greater than 200 wafers per hour. And that’s with a source power less than 100 watts and intermediate focus. The dose range for the source power is roughly 30 millijoule to 50 millijoule per centimeter squared.

Also at SPIE, TEL presented a paper on a novel integration scheme that enables EUV with double patterning for advanced nodes.

TEL has developed a bottom-up organic mandrel growth process, enabling EUV with self-aligned double patterning (SADP) for the sub-5nm nodes.

EUV is gaining steam in the market. In 2018, ASML’s 0.33 NA EUV scanners were inserted for production at 7nm. At 7nm, chipmakers are using EUV to pattern chip features with pitches starting at 40nm.

Vendors are using an EUV-based single patterning approach. The idea is to put the chip features on one mask and print them on the wafer using a single lithographic exposure.

Chipmakers want to extend EUV single patterning as far as possible, because it’s a straightforward process. EUV single patterning reaches the limit at around 30nm pitches, which represents the 5nm node or so.

At those pitches and beyond, roughly at the 3nm node, chipmakers need to look at new options, including EUV double patterning. In double patterning, you split the chip features on two masks and print them on the wafer. That’s complex and expensive, but it’s also something the fabs have mastered because EUV was delayed for so long.

In the fab, chipmakers may deploy a conventional EUV SADP flow using a series of deposition and etch steps. In this flow, a mandrel-like structure is patterned through a tri-layer stack. This is followed by a spacer etch and a mandrel pull process, resulting in a structure with pitch doubling, according to TEL.

“Standard EUV SADP flows involve the transfer of the resist through a lithography stack and into a hard mandrel material, such as silicon nitride or amorphous silicon. Achieving line edge roughness (LER) and line width roughness (LWR) targets for an EUV SADP hard mandrel is significantly more challenging than for EUV direct print since the etch process needs to target a post etch CD of about half that of the lithographic CD. This aggressive shrink requirement usually involves degradation in roughness driven by high aspect ratios,” according to a paper from four TEL researchers, Katie Lutker-Lee, Emma Richardson, David O’Meara and Angélique Raley, in the SPIE paper.

In response, TEL has developed a new process. The new integration scheme involves a bottoms up growth process of an organic mandrel. The mandrel is grown on top of the patterned photoresist, followed by spacer deposition, spacer etch, and mandrel pull, resulting in pitch doubling, according to TEL.

“The bottom-up grown organic mandrel integration scheme, starts with a simplified stack, where the resist is exposed directly or with the presence of an ARC material, such as BARC, on top of a patterning layer. This reduces the need for the deposition of a hard mandrel film, which is ultimately sacrificial,” according to the researchers from TEL in the paper. “After lithography, a selective organic mandrel deposition was performed in an etch chamber, growing the EUV photoresist to a height that is compatible with multi patterning. After the mandrel was formed, spacer deposition was performed using the same method as the conventional flow. Due to advances in the options available on the etch chamber, the spacer deposition has the potential to be performed in-situ, without ever leaving the etch chamber. This opens up the potential for an all in one process through a metal hard mask open in a single tool, without vacuum break.”

This process results in a 20nm pitch line-space pattern. “A process window for the mandrel growth was established that exhibits the ability to control the mandrel CD, roughness, profile, and across wafer uniformity,” according to the researchers from TEL.

Dry resists
At last year’s SPIE, Lam Research announced a dry resist technology for 3nm and beyond.

In Lam’s dry resist process, wafers are inserted in a dry resist deposition system. By combining various compounds, the deposition system creates an EUV resist in-situ. Then, the wafers are moved to an EUV scanner for exposure. Finally, the wafers move to a separate dry development system from Lam.

This process represents a 5X to 10X reduction in material waste and cost compared to spin coating.

At this year’s SPIE, Lam elaborated on the process. Here’s a blog on the technology.

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