Make The Impossible Possible: Use Variable-Shaped Beam Mask Writers And Curvilinear Full-Chip Inverse Lithography Technology For 193i Contacts/Vias With Mask-Wafer Co-Optimization

By eBeam Initiative - 22 Feb, 2024 - Comments: 0

Abstract: "Full-chip curvilinear inverse lithography technology (ILT) requires mask writers to write full reticle curvilinear mask patterns in a reasonable write time. We jointly study and present the benefits of a full-chip, curvilinear, stitchless ILT with mask-wafer co-optimization (MWCO) for variable-shaped beam (VSB) mask writers and validate its benefits on mask and wafer at Micron Tec... » read more

Looking Forward To SPIE, And Beyond

By Katherine Derbyshire - 16 Feb, 2023 - Comments: 0

On the eve of this year’s SPIE Advanced Lithography + Patterning conference, I took a look at the IEEE Devices and Systems Roadmap’s lithography section. It’s especially notable for the emergence of EUV lithography, which has quickly become critical for advanced logic. High-NA tools to support still smaller dimensions are on the horizon. In the near-term, though, the key challenge is not ... » read more

Chasing After Carbon Nanotube FETs

By Mark LaPedus - 18 Mar, 2021 - Comments: 6

Carbon nanotube transistors are finally making progress for potential use in advanced logic chips after nearly a quarter century in R&D. The question now is whether they will move out of the lab and into the fab. Several government agencies, companies, foundries, and universities over the years have been developing, and are now making advancements with carbon nanotube field-effect transi... » read more

Manufacturing Bits: March 8

By Mark LaPedus - 08 Mar, 2021 - Comments: 0

Two-beam EUV lithography At the recent SPIE Advanced Lithography conference, Nikon gave a presentation on a two-beam extreme ultraviolet (EUV) lithography technology. Still in the conceptual phase, Nikon’s so-called EUV Projection Optical Wafer Exposure Ruling Machine, or EUV Power Machine, is designed for the 1nm node or so. The proposed system has a minimum resolution of 10nm for lines ... » read more

Manufacturing Bits: March 2

By Mark LaPedus - 02 Mar, 2021 - Comments: 0

Next-gen AFM At the recent SPIE Advanced Lithography conference, Imec, Infinitesima and others described a new metrology tool technology called a Rapid Probe Microscope (RPM). Infinitesima has shipped its first RPM 3D system, enabling three-dimensional (3D) metrology applications for leading-edge chips. The system was jointly developed with Imec. In the IEDM paper, Imec and Infinitesima... » read more

Manufacturing Bits: March 3

By Mark LaPedus - 03 Mar, 2020 - Comments: 0

Security lithography At the recent SPIE Advanced Lithography conference, Multibeam disclosed more details about its efforts to develop multi-beam direct-write lithography for chip security applications. David Lam, chief executive and chairman of Multibeam, described how multi-beam lithography can be used to help thwart IC counterfeiting and tampering in the market. This lithography technolo... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

NAND Flash Targets 1,000 Layers

New techniques go beyond improved deposition and etching, but challenges stack up, too.

by Bryon Moyer

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.