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Chasing After Carbon Nanotube FETs

CNTs promise big performance improvements, but achieving consistency and replacing incumbent technologies will be difficult.


Carbon nanotube transistors are finally making progress for potential use in advanced logic chips after nearly a quarter century in R&D. The question now is whether they will move out of the lab and into the fab.

Several government agencies, companies, foundries, and universities over the years have been developing, and are now making advancements with carbon nanotube field-effect transistors (FETs), as well as newer versions integrated with memory. Carbon nanotubes are basically tiny rolled-up cylindrical sheets of graphene. But even though they exhibit better electrical and thermal properties than silicon, synthesizing high-purity tubes and integrating them into chips has been a major challenge. That’s why carbon nanotube FETs have been pushed out over the years, and are still not in mass production today.

Fig. 1: A carbon nanotube is essentially rolled up graphene, but all nanotubes are not the same. Source: NIST

In theory, though, carbon nanotube FETs can outperform today’s finFETs and perhaps other next-generation transistor types in R&D. Targeted for beyond the 3nm node or before, carbon nanotube FETs also are appealing because they resemble and operate like today’s conventional planar transistors, and may even extend planar to advanced nodes with immunity to short-channel effects. These devices are different than carbon nanotube RAMs, which are also in the works.

Like traditional transistors, which act like switches in devices, a carbon nanotube FET consists of a source, drain, and gate. The big difference is the channel, which allows electrons to flow from the source to the drain. In today’s transistors, the channel is based on silicon. In contrast, a carbon nanotube FET makes use of a fixed number of tiny and parallel nanotubes for the channels, each measuring 1nm in diameter. Leveraging the properties of these materials, carbon nanotube transistors exhibit high mobilities at low power.

Figure 2. A suspended carbon nanotube FET device. Source: Wikipedia

“It’s a very good transistor,” said H.-S. Philip Wong, a professor in the School of Engineering at Stanford. “We’ve done a lot of theoretical analysis as far as looking at isolated experiments of testing, managing transistors, and measuring performance. It does outperform conventional silicon transistors, if every piece comes together.”

In addition, carbon nanotube transistors are fabricated at lower temperatures. “That makes it possible to build things in 3D. Many memory type devices also can be made at low temperatures. So there is an opportunity to build chips in 3D with highly dense connections between the memory and the logic device,” Wong said.

On paper, this solves a major problem. In systems, data moves between the memory and a processor. But at times, this exchange causes latency and power consumption. Bringing the memory closer to the logic processing functions promises to address these issues. For this, nanotube chips aren’t the only answer. The industry is developing several different chip technologies to address the problem. Another option is to integrate memory and logic in an advanced package.

All told, the industry needs to watch all technologies, including carbon nanotubes. Here’s just a few breakthroughs in this area:

  • TSMC, Stanford, and the University of California at San Diego have developed a new material, paving the way toward robust carbon nanotube FETs for beyond 5nm.
  • Researchers from China have developed a process that enables high-density carbon nanotubes FETs.
  • A project led by DARPA is developing 3D devices, which stack memory on carbon nanotube transistors. The goal is to develop 3D devices on a 90nm process in 200mm fabs, which outperforms 7nm.

How to build a nanotube
Discovered in 1991, carbon nanotubes gained early attention, but the hype soon faded amid challenges with the technology. Today, carbon nanotubes are used in various industrial markets. However, they have barely made a dent in semiconductor applications.

In total, the carbon nanotube market is expected to grow from under $150 million in 2019/2020 to more than $500 million within the next decade, according to IDTechEx.

Based on carbon materials, carbon nanotubes come in various versions. Single-walled carbon nanotubes consists of one rolled-up sheet of graphene, while multi-walled carbon nanotubes incorporate several sheets. “In the past decade, the multi-wall market has been diverse and relatively niche,” said Richard Collins, a principal analyst at IDTechEx. “Some of the more notable applications have been in conductive polymers for the likes of automotive fuel systems and IC trays. There have been other success stories in elastomers, coatings, and energy storage, but these have been relatively small volumes.”

Carbon nanotube transistors are based on single-wall technology. “There are more potential advantages and a greater stepwise change rather than the iterative improvement of multi-wall. But the costs are high with limited capacity,” Collins said.

Nonetheless, there are several carbon nanotube material suppliers in the market. Carbon nanotubes are produced using several different methods, such as chemical vapor deposition (CVD), chromatography, and others.

A CVD system for nanotube production consists of a furnace, injection pump, and quartz substrate. In operation, the pump is filled with a carbon source material, injected into the furnace, and then heated. An inert gas is pumped into the reactor. The nanotube growth process occurs on the substrate.

Chromatography is a technique that separates a mixture. In a lab tool, a mixture of nanotubes is dissolved in a fluid, which is then carried through a column to different test tubes. The mixture travels at different velocities in the fluid, separating the superior semiconducting tubes from the metallic ones.

To develop carbon nanotube transistors, the first step is to synthesize nanotubes, and then integrate them into devices in a fab. Both steps are challenging.

This market began to heat up in 1998, when Delft University of Technology and IBM separately demonstrated the world’s first carbon nanotube FETs. Then, in 2006, IBM built the first circuit using nanotubes.

“At the time, the industry was still thinking about finding the next switch,” Stanford’s Wong said. “And that was the thinking, perhaps in early 2000, probably well into the first decade of 2000.”

During this period, device makers manufactured chips using traditional planar transistors. But there were fears that planar transistors would hit the wall at some point, meaning the industry would need a new technology.

That proved to be true. Planar transistors hit the wall at 20nm. But the industry selected finFETs as the next-generation transistor. FinFETs provide more performance at lower power than planar transistors, with less static leakage current.

In 2011, finFETs were introduced at 22nm, followed later at 16nm/14nm. Chipmakers have extended finFETs to 5nm. 3nm versions are slated for 2022/2023.

IBM and others continued to work on carbon nanotube transistors, but they were put on the backburner by many for several reasons. Let’s say a chip consists of a billion transistors. Each transistor may consist of 3 nanotubes, meaning a vendor must synthesize billions of high-purity tubes.

“The features of carbon nanotubes, including ballistic transport of electrons and a moderate intrinsic bandgap, made it a great candidate for being used in field-effect transistors and gas sensors,” said Ning Zhan, director of product marketing at Onto Innovation. “The electronic properties heavily depend on the structures. Current synthetic methods produce a mixture of structures, which includes both metallic materials with no bandgap and semiconductors with various bandgaps. Before we can have atomic-level structural control on a wafer-level scale, it will remain a challenge for CNTs to compete with existing materials in the semiconductor industry.”

Chipmakers are simply more comfortable using more mainstream technologies. For example, finFETs approach their limit when the fin width reaches 5nm, which equates to the 3nm node.

So at 3nm/2nm in 2023/2024, chipmakers are taking a more evolutionary step from finFETs, and embracing a next-generation transistor called gate-all-around (GAA) FETs. GAA promises to provide better performance than finFETs.

Still, the challenges are escalating at each node, and moving to a new transistor is difficult. “There are challenges for scaling, such as EPE margin, cost, high-aspect ratio patterning and Cs/Cb margin,” said Kazuya Okubo, vice president of integrated solution planning at TEL, during a presentation at SPIE Advanced Lithography. “Fundamental advances in memory and logic still rely on dimensional controllability in high-aspect patterns.”

It’s unclear how far the industry can extend GAA. This might be the last transistor type on the roadmap as chip scaling slows or grinds to a halt.

So today, many are looking for alternative approaches to develop new system-level designs. Advanced packaging is one of those approaches, and it is expected to continue gaining traction regardless of what happens with scaling.

In R&D, though, the industry is looking at several new transistor options if GAA runs out of steam beyond 2nm. Among those options are complementary FETs and nanotube transistors.

It’s unknown where nanotube chips fit into the equation. “I remain skeptical about the commercial prospects for nanotube transistors,” said David Fried, vice president of computational products at Lam Research. “The mobility values are pretty impressive, and improvements have been made to the contact properties. Interestingly, they seem to share the shape properties of nanowires. However, they’re competing against an incumbent device technology, where companies have spent many years and trillions of dollars figuring out how to consistently fabricate and pattern billions of transistors perfectly per chip across 300mm wafers. As far as I have seen, the challenges in uniformity and formation of nanotubes seem insurmountable to reach the level of expectations in silicon-based MOSFET technology.”

This is not to say carbon nanotube devices will never appear. “Nanotube transistors may find commercial opportunity in other realms of electronics,” Fried said. “Perhaps some alternate logic or memory technology could make use of their properties without the challenges of deterministic formation and patterning. They have potential for alternative applications requiring low-power devices or low temperature and flexible processing. These new applications could provide more opportunity than competing with silicon CMOS for high-density, high-performance applications.”

Prospects for nanotube FETs
Some are moving in that direction. Today, the industry is working on various carbon nanotube FET architectures, such as planar, double-gated and surround-gate or GAA. The planar versions are split into two camps—top-gated and bottom-gated. Doubled-gated versions resemble finFETs, while GAA involves a nanotube wrapped around a gate.

In the lab, carbon nanotubes transistors are moving in all directions. “Right now, there is no consensus,” Stanford’s Wong said. “In various publications, you see back-gated, top-gated, or wrapping around. A variety of configurations are possible.”

At the recent IEDM conference, meanwhile, TSMC, Stanford and UC San Diego presented a paper on a top-gated carbon nanotube FET with a 15nm gate length. Researchers also developed a new dielectric material here. Using this material, researchers see a path toward a top-gated carbon nanotube FET with a 10nm gate length and a 68mV/dec sub-threshold slope. The nanotubes are 1nm in diameter with 250 nanotubes/μm.

The resulting device from researchers resembles a planar transistor with palladium-based contacts and gate. “Carbon nanotube field-effect transistors are a candidate logic transistor to extend density, efficiency, and performance improvements beyond the limits of conventional silicon CMOS,” said Gregory Pitner, a principal engineer at TSMC, in a paper at IEDM.

While this work is promising, the hard part is synthesizing high-purity nanotubes without variations and integrating them into chips. “We are a little bit away from that, but not too far,” Stanford’s Wong said. “There are three things that you need — full wafer growth, density, and uniformity.”

In the nanotube FET process, a vendor must develop the nanotubes separately and then deposit them on a full wafer. Many have achieved that feat in the lab.

Then, on the wafer, the nanotubes must be uniform with high densities. “From a high-density point of view, there seems to be a potential solution,” Wong said. “Now, the remaining one is uniformity. That’s still an issue that is unresolved right now. How do you get highly uniform nanotubes next to each other?”

Still, TSMC, Stanford and UC San Diego have solved at least one major problem. They have found a way to form gate dielectrics on devices. Like today’s transistors, carbon nanotube FETs consist of a gate with high-k dielectric materials, which are used to mitigate leakage. In conventional transistors, high-k materials are deposited on the surface using atomic layer deposition (ALD).

In carbon nanotube FETs, though, ALD doesn’t nucleate on carbon surfaces, which presents a problem in developing the gate dielectrics. In response, researchers developed an interfacial layer dielectric composed of aluminum oxide. Using a low-temperature “nanofog” deposition method, the dielectric nucleates on the carbon surface, enabling high-k materials for the gate stack.

This material is incorporated during the carbon nanotube FET process from researchers. In a test structure, carbon nanotubes are first synthesized and aligned on a quartz substrate in a CVD system.

Then, on the substrate, the new dielectric materials are deposited on the nanotubes. Afterward, these materials and the nanotubes are removed from the outside regions. The middle portion still consists of the dielectric layer on top of the nanotubes, which forms the channels. Contacts are formed on the device. Then, for the gate dielectric, a layer of hafnium oxide is deposited. Finally, a gate electrode is formed.

Still, the challenge is to integrate these processes in the fab. Chipmakers don’t process chips on quartz substrates, but rather they use silicon wafers.

So in a realistic fab flow, the first step is to synthesize carbon nanotubes, which are then transferred onto a silicon wafer. Then, the wafer is processed using a conventional CMOS flow. The big difference is that ion implantation isn’t used during the flow. All of this is done at sub-400 °C.

Fig. 3: The process for fabricating a top-gated carbon nanotube FET. Source: Wikipedia

More tubes
In another breakthrough, meanwhile, Peking University, Xiangtan University and Zhejiang University last year reported on the development of high-density carbon nanotube arrays for logic devices.

Researchers synthesized the nanotubes using a chromatography sorting process. Then they developed a process that aligns carbon nanotube arrays on 4-inch wafers. The nanotube densities were 100 to 200 CNTs/μm, according to researchers in a paper in Science.

Using these processes, researchers developed five-stage ring oscillators based on a top-gated planar carbon nanotube FET with a sub-threshold slope of <90mV/dec.

“These CNT arrays meet the fundamental requirements for large-scale fabrication of digital ICs,” said Lijun Liu, a researcher from Peking University, in the paper.

Before they move out of the lab, the industry will need to scale up these processes on a larger wafer sizes like 200mm, particularly for sub-10nm nodes, according to researchers.

A U.S. collaboration is trying to accomplish that with a twist. In 2018, DARPA launched a new program called the Three Dimensional Monolithic System-on-a-Chip (3DSoC). MIT, Stanford and SkyWater are also part of the project.

The 3DSoC program hopes to develop a 3D device, which stacks ReRAM on a carbon nanotube transistor. ReRAM, a next-generation memory type, has lower read latencies and faster write performance than today’s flash memory. In ReRAM, a voltage is applied to a material stack, creating a change in the resistance that records data in the memory.

The goal is to develop a 3D device with 9 million interconnects/mm² for an aggregate bandwidth of 45Tb/s. This is said to deliver a 50X improvement in performance over a 7nm device, according to researchers.

That’s not the only technology in the works. Potentially, the process enables other forms of 3D devices that integrate logic, memory and other technologies. “Most people in the industry have come to the realization that the next switch is not going to save us,” Stanford’s Wong said. “If you think about the whole system, the transistor is only one piece of the equation. There are many other pieces of the equation. You need memory. You need to connect memory and logic together.”

Meanwhile, Skywater, the designated foundry in the 3DSoC project, is developing the processes to manufacture these and other technologies in a 200mm fab using 90nm processes. “If you look at advanced node silicon, we’re up against the fundamental laws of physics,” said Ross Miller, vice president of strategic marketing and business units at Skywater. “If you roll that forward and think about continued shrinkage of the geometries, there are things like leakage and power demand that are counterproductive to the whole pursuit. We need to find ways to continue to deliver performance to the market. What are the ways we can do that? There are many, but this particular one is focused on leveraging a new semiconductor material to in a sense reset Moore’s Law.”

Today, Skywater is in the second phase of the program, which runs through September 2021. The goal is to boost the manufacturability and yields of the technology.

Ultimately, Skywater hopes to provide design tools and foundry processes around the technology, enabling the development of devices for defense and commercial customers. Georgia Institute of Technology is developing the design tools here. No production date has been announced.

“That was the foundation of the initial program — to create a commercial foundry open accessible process technology that the industry has access to. It also involves aspects of design enablement. So PDK development and tools are needed for customers ultimately to engage with it,” Miller said.

In a recent paper in Nature Electronics, researchers outlined a process flow for the technology. The group is using chromatography to develop high-purity nanotubes.

In the fab, parts of the device are pre-patterned on a substrate. Then, using an “incubation” deposition process, the substrate is submerged in a carbon nanotube solution, which allows the tubes to adhere to the surface, according to the paper.

The incubation deposition approach uses existing 200mm wet processing stations in a fab. After the incubation step, the substrates are removed, rinsed with a solvent spray, and dried with nitrogen, according to the paper.

Making nanotube chips is only half the battle. A bigger challenge is getting customers to adopt a new technology. “From a technology perspective, there’s engineering work still ahead of us to mature this to the point that we can transact with it commercially,” Miller said. “How do we penetrate into these markets with paradigm shifting technology? That’s not a trivial task. And there’s work to educate about the potential and capabilities of this. There’s work to address potential reliability and quality concerns. There’s an education process to be done there. And there’s work to be done also to mature the supply chain.

IBM, Intel and others are dabbling with nanotube chips. Several universities are working on it.

On another front, Nantero is working on carbon nanotube RAMs. And Imec is developing graphene interconnects and carbon nanotube pellicles.

All of these are intriguing. But getting them off the ground will be difficult.

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Anonymous says:

Sounds like 90nm 3DSoC would outperform 7nm, 5nm, 3nm, 2nm, 1nm… or any other planar node. They expect the cost to be similar to TSMC 7nm.

Except there will be a huge performance drop off if the memory runs out and it has to go to external DRAM or storage. So I wonder how much memory they are targeting for the initial chips. 4 GB? 8 GB? It’s non-volatile, so if there’s enough for the OS and applications you wouldn’t have to go to storage as often. Soon we may be buying CPUs segmented based on the amount of L4 cache or stacked memory they have.

Diogene7 says:

I thought the same thing, that in a long term future (2030+), it may be that many 3DSoC chip will come with on board memory / storage.

In theory, if the claims from Nantero about their CNT RAM (NRAM) are not misleading, and NRAM power consumption is low, it should be possible to construct a full 3D Soc interleaving multiple layers of compute (CNT FET) + memory / storage (Nantero CNT memory) made mostly from Carbon Nanotubes, and those chips should be manufacturable at relatively low temperature (less than 200C / 400C).

Diogene7 says:

@Mark Lapedus: Thank you very much Mark for this great review of the state if development of post silicon electronics based on carbon nanotube (CNT FET) .

In My Humble Opinion (IMHO), as of 2021, it is one of the leading technology (with spintronics) that have the most likelyhood to follow suit after silicon transistor because it offer so many new disruptive opportunities that would be more complicated with silicon transistor (ex: CNT electronics on flexible substrate, low temperature manufacturing (less than 400C) of 3DSoC,…).

As of 2021, carbon nanotube electronics is probably at the same state of development like silicon electronics was in the 1950’s versus vacuum tubes : it is still in its early development stage.

I even believe that USA should take the opportunity to allocate significant engineering and financial ressources (billions of dollars) to speed up the manufacturability of the emerging post silicon technologies : CNT logic and memory, and spintronics to regain electronic leadership instead of attempting to catch-up with TSMC,… on leading edge sub 5nm chip manufacturing.

Any chance that you could interview Bill Gervasi from Nantero / Fujitsu about the state of development of NRAM and how it could fit in a carbon nanotube (CNFET) 3DSoC ?

My understanding is that, by now (March 2021), Fujitsu should be in High Volume Manufacturing (HVM) of chips that integrate NRAM as it was claimed it would be in HVM in 2020, but we didn’t heard from it since a while…

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