Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)

A technical paper titled “Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip” was published by researchers at University of Montpellier and University of Vale do Itajaí. Abstract: "Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables... » read more

Test Connections Clean Up With Real-Time Maintenance

Test facilities are beginning to implement real-time maintenance, rather than scheduled maintenance, to reduce manufacturing costs and boost product yield. Adaptive cleaning of probe needles and test sockets can extend equipment lifetimes and reduce yield excursions. The same is true for load board repair, which is moving toward predictive maintenance. But this change is much more complicate... » read more

Time To Pay The Piper

The Pied Piper of Hamelin is a German fable about a rat catcher who used his magic pipe to lure away rats. When he was not paid by the town, he used his pipe to lure away all of the town's children. I am not suggesting that exactly the same is true for the semiconductor industry and having not paid [getkc id="7" kc_name="EDA"], but I do not think they have paid enough and they will now have to ... » read more

User Defined Fault Models

This white paper describes the functionality of user defined fault models (UDFM), including gate exhaustive UDFM and cell-aware UDFM, and the effectiveness of lowering DPM in devices. To achieve today's quality and defect-per-million (DPM) goals, high-quality testing must achieve very high defect coverage. Testing today typically consists of generating test patterns based on multiple fault m... » read more