More Choices, Less Certainty

By Ed Sperling - 04 Nov, 2015 - Comments: 3

The increasing cost of feature scaling is splintering the chip market, injecting uncertainty into a global supply chain that has been continually fine-tuned for decades. Those with deep enough resources and a clear need for density will likely follow Moore's Law, at least until 7nm. What comes after that will depend on a variety of factors ranging from available lithography—EUV, multi-bea... » read more

Increasing Challenges At Advanced Nodes

By Ed Sperling - 22 Oct, 2015 - Comments: 1

Gary Patton, chief technology officer at GlobalFoundries, sat down with Semiconductor Engineering to talk about new materials, stacked die, how far FD-SOI can be extended, and new directions for interconnects and transistors. What follows are excerpts of that conversation. SE: Where do you see problems at future nodes? Patton: At the device level, we have to be able to pattern these thing... » read more

Accurate Thermal Analysis, Including Thermal Coupling Of On-Chip Hot Interconnect

By Norman Chang - 15 Oct, 2015 - Comments: 0

Driven by rapid advancement in mobile/server computing and automotive/communications, SoCs are experiencing a fast pace of functional integration along with technology scaling. Advanced low power techniques are widely used, while meeting higher performance requirements using a variety of packaging technologies. The Internet of Things (IoT) is further opening up new applications with connected d... » read more

The Week In Review: Manufacturing

By Mark LaPedus - 09 Oct, 2015 - Comments: 0

Is the sky falling in the IC equipment market? Not yet, but watch out below. Semi capital spending is expected to reach $60.37 billion in 2015, down 1% from 2014, according to Pacific Crest Securities. “Although we trimmed 2016 capex three weeks ago, we are trimming some more. We now see semiconductor capex down 4% in 2016. However, we do not see capex falling off a cliff in 2016 (i.e., down ... » read more

Executive Insight: Lip-Bu Tan

By Ed Sperling - 01 Oct, 2015 - Comments: 1

Lip-Bu Tan, president and CEO of Cadence, sat down with Semiconductor Engineering to talk about consolidation, Moore's Law, and where the opportunities are in the IoT and automotive markets. What follows are excerpts of that conversation. SE: What are the big concerns for the semiconductor industry in general, and EDA in particular? Tan: Top on my list is all the consolidation that's goin... » read more

Raise A Fence, Dig A Tunnel, Build A Bridge

By Ed Sperling - 17 Sep, 2015 - Comments: 0

There are three main options for chipmakers over the course of the next decade. Which option they choose depends upon their individual needs, talents, and how much and what kind of differentiation they believe will matter to them. The options roughly fall into three categories—fence, bridge or tunnel. The fence option Rather than changing anything, the entire ecosystem can stick to wha... » read more

Challenges At Advanced Nodes

By Ed Sperling - 09 Sep, 2015 - Comments: 0

Semiconductor Engineering sat down to discuss finFETs, 22nm FD-SOI and how the how the market will segment over the next few years with Marie Semeria, CEO of [getentity id="22192" e_name="Leti"]; Patrick Soheili, vice president of product management and corporate development at [getentity id="22242" e_name="eSilicon"]; Paul Boudre, CEO of Soitec; and Subramani Kengeri, vice president of global ... » read more

Executive Insight: Sanjiv Kaul

By Ed Sperling - 02 Sep, 2015 - Comments: 0

Sanjiv Kaul, president and CEO of [getentity id="22016" e_name="Calypto"], sat down with Semiconductor Engineering to talk about dynamic power concerns in finFETs, where software fits in, and why high-level synthesis is now a competitive requirement at advanced nodes. What follows are excerpts of that conversation. SE: What's the biggest problem the semiconductor industry is facing right no... » read more

What Works After 7nm?

By Mark LaPedus - 20 Aug, 2015 - Comments: 3

An Steegen, senior vice president of process technology at [getentity id="22217" e_name="Imec"], the Belgium-based R&D organization, sat down with Semiconductor Engineering to discuss the future of process technology and transistor trends all the way to 3nm. SE: Some say the semiconductor industry is maturing. Yet we have more device types and options than ever before, right? Steegen:... » read more

Challenges At Advanced Nodes

By Ed Sperling - 19 Aug, 2015 - Comments: 0

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tag: FD-SOI

More Choices, Less Certainty

Increasing Challenges At Advanced Nodes

Accurate Thermal Analysis, Including Thermal Coupling Of On-Chip Hot Interconnect

The Week In Review: Manufacturing

Executive Insight: Lip-Bu Tan

Raise A Fence, Dig A Tunnel, Build A Bridge

Challenges At Advanced Nodes

Executive Insight: Sanjiv Kaul

What Works After 7nm?

Challenges At Advanced Nodes