tag: FD-SOI

Shootout At 28nm
By Ed Sperling - 15 May, 2014 - Comments: 0

By Ed Sperling & Mark LaPedus Samsung, Soitec and STMicroelectronics are joining forces on 28nm FD-SOI, creating a showdown with TSMC and others over the best single-patterned processes and materials and raising questions about how quickly companies need to move to the finFET technology generation. The multi-source manufacturing collaboration agreement for fully depleted silicon-on-insulato... » read more

Power Moves Up To First Place
By Ed Sperling - 10 Apr, 2014 - Comments: 2

Virtually every presentation delivered about semiconductor design or manufacturing these days—and every end product specification that uses advanced technology—incorporates some reference to power and/or energy. It has emerged as the most persistent, most problematic, and certainly the most talked about issue from conception to marketplace adoption. And the conversation only grows louder... » read more

Fastest Computers On The Planet
By Barry Pangrle - 05 Dec, 2013 - Comments: 0

The latest Green500 list (Excel spreadsheet here) was just released at the end of last month and heterogeneous systems now own the top of the list. The Top 10 systems all use a combination of Intel Xeon (mostly E5) processors paired with NVIDIA K20s. There are now 6 systems listed that have broken the 3,000 MFLOPS/W barrier and TSUBAME-KFC, belonging to the Tokyo Institute of Technology’s GSI... » read more

Seven Ways To Improve PPA Before Moving To FinFETs
By Ed Sperling - 05 Dec, 2013 - Comments: 0

Henry Ford wrote in his autobiography, “Any customer can have a car painted any color that he wants so long as it is black.” And for decades, the semiconductor industry has marched to a similar theme set by Moore’s Law. But with the transition to finFETs harder than it first appeared, questions are beginning to pop up that is fueling a new level of confusion. While the growing list of... » read more

ARM Cortex-A53, UPF & FD-SOI
By Barry Pangrle - 07 Nov, 2013 - Comments: 0

The IEEE Standards Association Symposium on Electronic Design Automation (EDA) Interoperability was held on Oct. 24. I found the first session, Interoperability Challenges: Power Management in Silicon, with presentations by Erich Marschner of Mentor Graphics and Stuart Riches and Adnan Khan (both from ARM) to be particularly interesting. Earlier this year, the IEEE announced a new version of UP... » read more

Uncertainty, But Not Over Power
By Ed Sperling - 25 Oct, 2013 - Comments: 0

The semiconductor industry has reached a crossroads. Lithography has stalled out, NRE is rising, and chipmakers are torn between choices of when and whether to jump to the next process node—and even more daunting, the next one after that—or whether to take half steps with fan outs, 2.5D, or fully depleted SOI. While chips do continue to tape out, the number of critical choices that need... » read more

Week In Review: Manufacturing & Design
By Mark LaPedus - 25 Oct, 2013 - Comments: 0

Don’t look now, but Intel is expanding its foundry business. Previously, Intel garnered a small collection of foundry customers. But Intel would not entertain foundry customers that had competitive products based on ARM chips. Apparently, Intel is having a change of heart. “I think they’ve changed their position,” said Nathan Brookwood, a research fellow at Insight 64. “They will do A... » read more

The Week In Review: Oct. 4
By Mark LaPedus - 04 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling eSilicon introduced an automated multi-project wafer quote system, which allows companies to sort through a number of options and get pricing. The quotes are tied into TSMC's 20nm to 350nm processes, and GlobalFoundries’ 20nm to 180nm processes. The approach eliminates the need for companies to buy a full wafer if their volume requirements don’t warrant it... » read more

Viable Choices Ahead
By Ed Sperling - 27 Sep, 2013 - Comments: 0

Two years ago—basically one process node back, wherever companies were on the Moore’s Law road map—there was confusion about what lies ahead and what is the best way to proceed. During that time, three very viable options have been proven to work. Some already are in silicon, while others are coming very soon. The first is the finFET. At the very leading edge of the road map, finFET... » read more

Executive Briefing: Soitec CEO
By Mark LaPedus - 19 Sep, 2013 - Comments: 0

By Mark LaPedus Semiconductor Manufacturing & Design sat down to discuss FD-SOI, solar and various technology trends with André-Jacques Auberton-Hervé, chairman and chief executive of Soitec, a supplier of silicon-on-insulator (SOI) substrates, solar concentrators and other products. SMD: The digital process roadmap is moving in several directions. Some pure-play foundries will offer ... » read more

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