tag: finFETs

Patterning Problems Pile Up
By Mark LaPedus - 20 Mar, 2017 - Comments: 4

Chipmakers are ramping up 16nm/14nm finFET processes, with 10nm and 7nm now moving into early production. But at 10nm and beyond, chipmakers are running into a new set of problems. While shrinking feature sizes of a device down to 10nm, 7nm, 5nm and perhaps beyond is possible using current and future fab equipment, there doesn't seem to be a simple way to solve the edge placement error (EPE)... » read more

China: Fab Boom or Bust?
By Mark LaPedus - 16 Mar, 2017 - Comments: 2

China’s semiconductor industry continues to expand at a frenetic pace. At present there are nearly two dozen new fab projects in China. Whether all these fab projects get off the ground is not entirely clear because the dynamics in China remain fluid. What is clear is the motivation behind this building frenzy—China is trying to reduce its huge trade imbalance in ICs. The country continu... » read more

Power Impacting Cost Of Chips
By Brian Bailey - 15 Mar, 2017 - Comments: 0

The increase in complexity of the power delivery network (PDN) is starting to outpace increases in functional complexity, adding to the already escalating costs of modern chips. With no signs of slowdown, designers have to ensure that overdesign and margining do not eat up all of the profit margin. The semiconductor industry is used to problems becoming harder at smaller geometries, but unti... » read more

Battling Fab Cycle Times
By Mark LaPedus - 16 Feb, 2017 - Comments: 9

The shift from planar devices to finFETs enables chipmakers to scale their processes and devices from 16nm/14nm and beyond, but the industry faces several challenges at each node. Cost and technical issues are the obvious challenges. In addition, cycle time—a key but less publicized part of the chip-scaling equation—also is increasing at every turn, creating more angst for chipmakers and... » read more

Changing Direction In Chip Design
By Ed Sperling - 26 Jan, 2017 - Comments: 1

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

What’s Next For Transistors
By Mark LaPedus - 23 Jan, 2017 - Comments: 1

The IC industry is moving in several different directions at once. The largest chipmakers continue to march down process nodes with chip scaling, while others are moving towards various advanced packaging schemes. On top of that, post-CMOS devices, neuromorphic chips and quantum computing are all in the works. Semiconductor Engineering sat down to discuss these technologies with Marie Semeri... » read more

China Unveils Memory Plans
By Mark LaPedus - 19 Jan, 2017 - Comments: 2

Backed by billions of dollars in government funding, China in 2014 launched a major initiative to advance its domestic semiconductor, IC-packaging and other electronic sectors. So far, though, the results are mixed. China is making progress in IC-packaging, but the nation’s efforts to advance its domestic logic and memory sectors are still a work in progress. In fact, China has yet to achi... » read more

FinFET And Multi-Patterning Aware Place-And-Route Implementation
By Mentor, a Siemens Business - 18 Jan, 2017 - Comments: 0

The use of finFETs and multi-patterning has a huge impact on the entire physical implementation flow. This paper outlines the new challenges in placement, routing, optimization, and physical verification and describes how the Nitro-SoC place and route system handles them. To read more, click here. » read more

Choosing Power-Saving Techniques
By Ann Mutschler - 16 Jan, 2017 - Comments: 1

Engineers have come up with a long list of ways to save power in chip and system designs, but there are few rules to determine which approaches work best for any given design. There is widespread confusion about what techniques should be used where, which IP or subsystem is best, and how everything should be packaged together. The choices include everything from the proper level of clock and... » read more

Reflecting Back On 2016
By Brian Bailey - 22 Dec, 2016 - Comments: 0

Anyone can make a prediction, and sometimes the more outlandish they are the more they get noticed. But at the end of the year some people hit the mark while others may have been way off. Many people simply make projections based on the current trajectory of trends, while others look for the potential discontinuities that may lie ahead. Semiconductor Engineering examines the projections made... » read more

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