tag: finFETs

Etching Technology Advances
By Jeff Dorsch - 15 Dec, 2016 - Comments: 0

Let’s get really, really small. That directive from leading semiconductor companies and their customers is forcing the whole semiconductor supply chain to come up with new ways to design and manufacture ever-shrinking dimensions for chips. The current push is to 10nm and 7nm, but R&D into 5nm and 3nm is already underway. To put this in perspective, there are roughly two silicon atom... » read more

Tech Talk: FD-SOI vs. FinFET
By Ed Sperling - 15 Dec, 2016 - Comments: 0

Jamie Schaeffer, 22FDX program director at GlobalFoundries, talks about the future of FD-SOI, what the tradeoffs are in performance, power and cost compared with finFETs, how many mask layers and patterning steps are required for each, and when 12nm FD-SOI will be introduced. Related Stories To 7nm And Beyond GlobalFoundries’ top technologists open up on next-gen FD-SOI, the economi... » read more

Timing Closure Issues Resurface
By Ed Sperling - 07 Dec, 2016 - Comments: 1

Timing closure has resurfaced as a major challenge at 10nm and 7nm due to more features and power modes, increased process variation and other manufacturing-related issues. While timing-related problems are roughly correlated to rising complexity in semiconductors, they tend to generate problems in waves—about once per decade. In SoCs, timing closure problems have spawned entire methodolog... » read more

7nm Design Success Starts With Multi-Domain Multi-Physics Analysis
By Arvind Vel - 28 Nov, 2016 - Comments: 1

Companies can benefit from advancements in the latest semiconductor process technology by delivering smaller, faster and lower power products, especially for those servicing mobile, high performance computing and automotive ADAS applications. By using 7nm processes, design teams are able to add a lot more functionality onto a single chip and lower the power consumption by scaling operating volt... » read more

Multi-Patterning Issues At 7nm, 5nm
By Ed Sperling - 28 Nov, 2016 - Comments: 13

Continuing to rely on 193nm immersion lithography with multiple patterning is becoming much more difficult at 7nm and 5nm. With the help of various resolution enhancement techniques, optical lithography using a deep ultraviolet excimer laser has been the workhorse patterning technology in the fab since the early 1980s. It is so closely tied with the continuation of [getkc id="74" comment="Mo... » read more

Can We Measure Next-Gen FinFETs?
By Mark LaPedus - 21 Nov, 2016 - Comments: 6

After ramping up their respective 16nm/14nm finFET processes, chipmakers are moving towards 10nm and/or 7nm, with 5nm in R&D. But as they move down the process roadmap, they will face a new set of fab challenges. In addition to lithography and interconnects, there is metrology. Metrology, the science of measurements, is used to characterize tiny films and structures. It helps to boost yi... » read more

Measuring Atoms And Beyond
By Mark LaPedus - 21 Nov, 2016 - Comments: 0

David Seiler, chief of the Engineering Physics Division within the Physical Measurement Laboratory at the National Institute of Standards and Technology (NIST), sat down with Semiconductor Engineering to discuss the current and future directions of metrology. NIST, a physical science laboratory, is part of the U.S. Department of Commerce. What follows are excerpts of that conversation. SE: W... » read more

Partitioning For Power
By Ed Sperling - 14 Nov, 2016 - Comments: 0

Examine any smartphone design today and most of the electronic circuitry is "off" most of the time. And regardless of how many processor cores are available, it's rare to use more than a couple of those cores at any point in time. The emphasis is shifting, though, as the mobility market flattens and other markets such as driver-assisted vehicles and IoT begin gaining traction. In a car, turn... » read more

Moore’s Law Debate Continues
By Ann Mutschler - 02 Nov, 2016 - Comments: 0

Does shrinking devices still make sense from a cost and performance perspective? The answer isn’t so simple anymore. Still, the discussion as to whether semiconductors are still on track with [getkc id="74" comment="Moore's Law"] occurs on a frequent enough basis to continue analyzing at least some of the dynamics at play. There is much speculation about what happens after 7nm, as well as ... » read more

FinFET Front-End-of-Line (FEOL) Process Integration With SEMulator3D
By Coventor - 19 Oct, 2016 - Comments: 0

Purely geometric scaling of transistors ended around the 90-nanometer (nm) era. Since then, most power/performance and area/cost improvements have come from structural and material innovations. Silicon-on-Insulator (SOI), first “partially depleted” and more recently “fully depleted” as well as embedded stressors, High-K / Metal-Gate (HKMG) and now FinFETs are examples of technology inno... » read more

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