tag: finFETs

Stacked Die Changes
By Ed Sperling - 27 Jul, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

To 7nm And Beyond
By Ed Sperling - 21 Jul, 2016 - Comments: 4

Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], and Thomas Caulfield, senior vice president and general manager of Fab 8, sat down with Semiconductor Engineering to discuss future directions in technology, including the next rev of FD-SOI, the future of Moore’s Law, and how some very public challenges will likely unfold. SE: What do you see as the... » read more

Executive Insight: Aart de Geus
By Ed Sperling - 20 Jul, 2016 - Comments: 0

Aart de Geus, chairman and co-CEO of Synopsys, sat down with Semiconductor Engineering to discuss Moore's Law, the IoT, inflection points and how chip design will evolve in coming years. SE: We are in the middle of possibly one of the biggest transition points we’ve ever seen in this industry. How do you envision things shaking out? De Geus: There is no question that there is an enormou... » read more

SoC Power Grid Challenges
By Brian Bailey - 14 Jul, 2016 - Comments: 7

The consumption of power and dissipation of heat within large SoCs has received a lot of attention recently, but that is only part of the issue. Power also has to be reliably delivered onto and around the system. This is becoming increasingly difficult, and new nodes are adding to the list of challenges. "If we were building chips where there was only a single Vdd and Vss then it is not that... » read more

Implementation Limits Power Optimization
By Ann Mutschler - 14 Jul, 2016 - Comments: 3

Implementation is still the step that makes or breaks power budgets in chip design, despite improvements in power estimation, power simulations, and an increase in the number of power-related architectural decisions. The reason: All of those decisions must be carried throughout the design flow. “If implementation decides to give up, then it doesn't really matter at the end of the day,” s... » read more

Near-Threshold Computing
By Brian Bailey - 16 Jun, 2016 - Comments: 2

The emergence of the Internet of Things (IoT) has brought a lot of attention to the need for extremely low-power design, and this in turn has increased the pressure for voltage reduction. In the past, each new process node shrunk the feature size and lowered the nominal operating voltage. This resulted in a drop in power consumption. However, the situation changed at about 90nm in two ways. ... » read more

An Introduction to Reducing Dynamic Power Using PowerPro
By Mentor, a Siemens Business - 14 Jun, 2016 - Comments: 0

At many companies, the job of power reduction is left to power experts. These experts have built up knowledge and methodologies over many years, which they repeatedly apply to designs in their groups. This approach is very narrow and it not scalable across multiple groups in the company. Companies have begun to realize the limitations of this approach. More and more RTL designers are being task... » read more

Pathfinding Beyond FinFETs
By Paula Doe - 13 Jun, 2016 - Comments: 0

Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

Plotting The Next Semiconductor Road Map
By Ed Sperling - 13 Jun, 2016 - Comments: 0

The semiconductor industry is retrenching around new technologies and markets as Moore's Law becomes harder to sustain and growth rates in smart phones continue to flatten. In the past, it was a sure bet that pushing to the next process node would provide improvements in power, performance and cost. But after 22nm, the economics change due to the need for multi-patterning and finFETs, and th... » read more

One-On-One: Dave Hemker
By Ed Sperling - 19 May, 2016 - Comments: 0

Dave Hemker, CTO at [getentity id="22820" comment="Lam Research"], sat down with Semiconductor Engineering to look at some of the key issues on the process and manufacturing side, and some of the key developments that will reshape the semiconductor industry in the future. What follows are excerpts of that conversation. SE: One of the big discussion topics these days is [getkc id="208" commen... » read more

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