tag: finFETs

Improving 2.5D Components
By Ed Sperling - 07 Aug, 2014 - Comments: 1

A lot of attention is being focused on improving designs at established, well-tested nodes where processes are mature, yields are high, and costs are under control. So what does this mean to stacking die? For 2.5D architectures, plenty. For 3D, probably not much. Here’s why: The advantage of 2.5D is that it can utilize dies created at whatever node makes sense. While the initial discuss... » read more

Power Reduction Techniques
By Mary Ann White - 07 Aug, 2014 - Comments: 0

As 16nm and 14nm finFET process nodes come into production toward the end of this year, the performance (up to 30% vs. 28nm planar CMOS), power (~30%) and area (up to ~50%) benefits have been well documented. The same can be said for the 28nm FD-SOI process as it gains more traction in the marketplace touting similar performance and power improvements as those for FinFET when compared against i... » read more

Established Nodes Getting New Attention
By Ed Sperling - 07 Aug, 2014 - Comments: 0

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors. The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

Changing The Meaning Of Sign-Off
By Muhammad Zakir - 07 Aug, 2014 - Comments: 0

Chip development teams are faced with an ever-increasing number of power integrity and reliability challenges these days, especially as designs adopt FinFET technology. Even those with the most thorough sign-off checks often encounter unexpected surprises that quickly turn into tape-out hurdles, or worse yet, extensive re-design. The best way to avoid this scenario and ensure a smoother sign-of... » read more

System-Aware SoC Power, Noise And Reliability Sign-Off
By Ansys - 06 Aug, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 31 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta. What follows are excerpts of that conversation. SE: It’s harder for a fabless semiconductor ... » read more

EDA’s Hedge Plays
By Ed Sperling - 24 Jul, 2014 - Comments: 0

While 14/16nm process technologies with finFETs and double patterning have pushed complexity to new heights, the move to 10nm fundamentally will change a number of very basic elements of the design through manufacturing flow—and EDA vendors will be caught in the middle of having to make hard choices between foundries, processes, packaging approaches, and potentially which markets to serve. ... » read more

High-Level Gaps Emerge
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 21 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation. SE: What happens with the next revs of finFET... » read more

Confusion Does Not Equal Paralysis
By Ed Sperling - 10 Jul, 2014 - Comments: 0

After attending the two biggest semiconductor conferences in the world, along with a long list of notable conferences targeted to a wide variety of technologies and engineering disciplines, it’s clear the industry is racing ahead. But “ahead” is now a relative term. While Moore’s Law satisfied both economic and technological requirements, it was easy to figure out what “ahead” me... » read more

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