tag: finFETs

High-Level Gaps Emerge
By Ann Mutschler - 24 Jul, 2014 - Comments: 0

Semiconductor Engineering sat down to discuss the attributes of a high-level, front-end design flow, and why it is needed at present with Leah Clark, associate technical director for digital video technology at Broadcom; Jon McDonald, technical marketing engineer at Mentor Graphics; Phil Bishop, vice president of the System Level Design System & Verification Group at Cadence; and Bernard Mu... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 21 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics, and Bernard Murphy, CTO of Atrenta;. What follows are excerpts of that conversation. SE: What happens with the next revs of finFET... » read more

Confusion Does Not Equal Paralysis
By Ed Sperling - 10 Jul, 2014 - Comments: 0

After attending the two biggest semiconductor conferences in the world, along with a long list of notable conferences targeted to a wide variety of technologies and engineering disciplines, it’s clear the industry is racing ahead. But “ahead” is now a relative term. While Moore’s Law satisfied both economic and technological requirements, it was easy to figure out what “ahead” me... » read more

IP And FinFETs At Advanced Nodes
By Ed Sperling - 10 Jul, 2014 - Comments: 2

Semiconductor Engineering sat down to discuss IP and finFETs at advanced nodes with Bernard Murphy, CTO of Atrenta; Warren Savage, president and CEO of IPextreme; Aveek Sarkar, vice president of engineering and product support at Ansys-Apache; Randy Smith, vice president of marketing at Sonics. What follows are excerpts of that conversation. SE: As we push into the next nodes, we’ve got a ... » read more

Supporting LP In New Process Nodes
By Ann Mutschler - 10 Jul, 2014 - Comments: 0

Manufacturing process nodes and EDA tools are advancing all the time, but not always utilized at the same pace. And from a tools perspective, there are challenges to supporting low power in new process nodes while maintaining and improving the existing process nodes. One way design teams address this is by leveraging the most advanced software on the less-than-bleeding edge designs. To th... » read more

FinFET Based Designs: Reliability Verification Implications
By Aveek Sarkar - 10 Jul, 2014 - Comments: 1

Over the past few months, I’ve discussed various challenges associated with finFET-based designs. We all know that finFET devices enable design teams to operate their chips at significantly lower supply voltages with a very tight control on leakage current. But to control the overall power within a tight power budget, the challenge shifts to how the logic design is managed such that the overa... » read more

28nm FinFETs?
By Brian Bailey - 10 Jul, 2014 - Comments: 5

One star of the upcoming 14/16nm process node is the introduction of the finFET, a fundamentally new transistor that overcomes many of the limitations associated with planar transistors. While these devices are more complex to construct—and the physical extraction processes associated with them is more complex due to an increased number of resistances and capacitances—they are seen as a tra... » read more

System-Aware SoC Power, Noise And Reliability Signoff
By Ansys - 09 Jul, 2014 - Comments: 0

In globally competitive markets for mobile, consumer and automotive electronic systems, the critical success factors are power consumption, performance and reliability. To manage these conflicting requirements, design teams consider multiple options, including the use of advanced process technology nodes — especially FinFET-based devices. These advanced technology nodes allow chips to operate... » read more

Why An IBM Sale Matters
By Ed Sperling - 07 Jul, 2014 - Comments: 0

The rumored sale of IBM’s semiconductor unit to GlobalFoundries could add some interesting capabilities for the foundry, including deep process technology and expertise. It also could have some far-reaching effects for the entire semiconductor industry. The reason revolves around ongoing U.S. government initiatives to improve visibility for components throughout its supply chain. IBM has b... » read more

Semiconductor R&D Crisis Ahead?
By Ed Sperling - 26 Jun, 2014 - Comments: 0

Listen to engineering management at chipmakers these days and a consistent theme emerges: They’re all petrified about where to place their next technology bets. Do they move to 14/16nm finFETs with plans to shrink to 10nm, 7nm and maybe even 5nm? Do they invest in 2.5D and 3D stacked die? Or do they eke more from existing process nodes using new process technologies, more compact designs and ... » read more

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