tag: formal verification

The New Verification Landscape
By Ed Sperling - 27 Jun, 2013 - Comments: 0

By Ann Steffora Mutschler Verification technologies and tools have never been more sophisticated. But putting together a methodology is more than just putting tools together. It starts with trying to get a handle on the complexity, knowing what to test, how to test and when. “UVM was standardized and people have been working to adopt that which has been generally a positive,” said Steve Ba... » read more

Executive Briefing: Formal Attire
By Ed Sperling - 06 Jun, 2013 - Comments: 0

Kathryn Kranen, CEO of Jasper Design Automation, talks with Low Power-High-Performance Engineering about formal verification, where the pain points are in SoC design, and why there is still life left in Moore's Law. [youtube vid=x4jlo6_RRqw] » read more

Shifts In Verification
By Ed Sperling - 25 Apr, 2013 - Comments: 0

By Ann Steffora Mutschler Verifying an SoC requires a holistic view of the system, and engineering teams use a number of tools to reach a high degree of confidence in the coverage. But how and when to use those tools is in flux as engineering teams wrestle with increasing complexity at every level of the design, and a skyrocketing increase in the challenge of verifying it. There are no ... » read more

Is This The Era Of Automatic Formal Checks For Verification?
By Graham Bell - 28 Feb, 2013 - Comments: 0

I was thinking about the above question and recalled something IBM would repeat annually back in the late 1980s about its OS/2 replacement for MS-DOS. “This is the year of OS/2!” they would shout. But the marketplace wasn’t listening. As one buddy of mine liked to say, it was only half of an operating system (O.S./2). In the last nine months, my company, Real Intent, along with our com... » read more

PSL/SVA Assertions In SPICE
By Various Writers - 28 Jun, 2012 - Comments: 0

Assertion-based verification is a key aspect of any complete SoC or Silicon Realization flow. In this paper, we discuss how PSL (Property Specification Language)/SVA (System-V erilog Assertions) assertion semantics are extended for the first time to SPICE (Simulation Program with Integrated Circuit Emphasis)-level netlists and evaluated within a SPICE simulator, and present multiple examples an... » read more

Getting Formal With Power
By Ed Sperling - 14 Jun, 2012 - Comments: 0

By Ed Sperling Formal methodologies have always been an important tool in the verification engineer’s toolbox because they often can pinpoint bugs faster and with more accuracy than other verification approaches. The problem is that most engineers don’t know how to use them, and understanding this technology to a proficiency level requires a learning curve that most engineers consider pain... » read more

Understanding Formal Verification Concepts, Part 3
By Various Writers - 20 Oct, 2011 - Comments: 0

This final white paper in a three-part series about formal verification concepts examines the assertion-based verification flow and some of the formal verification algorithms. To download the first two papers in this series, click here for part one and here for part two. This kind of approach has become necessary as SoC designs become more challenging and the traditional method of simulat... » read more

Understanding Formal Verification Concepts, Part II
By Various Writers - 28 Jul, 2011 - Comments: 0

In this second white paper in a three-part series about formal verification concepts, we examine the assertion-based verification flow and some of the formal verification algorithms. This kind of approach has become necessary as SoC designs become more challenging and as the traditional method of simulation proves too slow, too costly, and insufficient in terms of coverage. To downoload thi... » read more

Understanding Formal Verification Concepts
By Various Writers - 28 Apr, 2011 - Comments: 0

In today’s complex system on chip (SoC) designs, verification has become a real challenge. Register transfer level (RTL) and gate-level simulations are effectively used for verifying the functional correctness of any design. However, as designs are growing in size as well as functionality, more and more test vectors need to be created and run to get reasonable test coverage. In addition to th... » read more

Why So Formal?
By Bhanu Kapoor - 21 May, 2010 - Comments: 0

By Bhanu Kapoor Let’s take a look at the types of power management verification issues that are most suited for formal verification and how formal techniques complement dynamic simulation-based verification in some of the challenging tasks associated with validating SoC power management architectures. There are three main categories of formal tools in use today: Equivalence Checkers, Asse... » read more

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