tag: formal verification

New Uses For Assertions
By Ann Mutschler - 24 Sep, 2020 - Comments: 0

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Formal Solutions For SystemC/C++ Verification
By OneSpin Solutions - 23 Sep, 2020 - Comments: 0

OneSpin Solutions provides its popular 360 DV formal verification product line, which allows for both the automated checking and full assertion-based verification of SystemC/C++ design representations. This solution extends the verification capability that may be applied to abstract designs, coded in SystemC/C++ for many different use models. This white paper describes the OneSpin solution a... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

Components For Open-Source Verification
By Brian Bailey - 02 Sep, 2020 - Comments: 2

Defining an open-source verification methodology is a lot more difficult than just developing an open-source simulator. This is the reality facing open-source hardware such as RISC-V. Some people may be asking for the corresponding open-source verification, but that is a much tougher problem — and it is not going to be solved in the short term. Part one examined the reasons why open-source... » read more

Creating Better Models For Software And Hardware Verification
By Ed Sperling - 04 Aug, 2020 - Comments: 1

Semiconductor Engineering sat down to discuss what's ahead for verification with Daniel Schostak, Arm fellow and verification architect; Ty Garibay, vice president of hardware engineering at Mythic; Balachandran Rajendran, CTO at Dell EMC; Saad Godil, director of applied deep learning research at Nvidia; Nasr Ullah, senior director of performance architecture at SiFive. What follows are excerpt... » read more

Real Highlights For Virtual DAC 2020
By Sergio Marchese - 25 Jun, 2020 - Comments: 0

My first time at DAC was in 2006 in San Francisco. I was mesmerized by it: so many people, so much cool technology, so much fun with weird giveaways, raffles, happy hours, the Denali party and Disco Inferno at the legendary Fillmore. DAC is the most important, comprehensive conference for anyone developing integrated circuits (ICs) and systems-on-chips (SoCs). With an incredible list of ... » read more

Rethinking Your Approach To Radiation Mitigation
By Mentor, a Siemens Business - 03 Jun, 2020 - Comments: 0

Formal verification and automation provide an effective, high quality, and repeatable process for fault analysis, protection, and verification for FPGA designs used in high radiation environments. This paper describes an automated systematic approach based on formal verification structural and static analysis that identifies design susceptibility to radiation induced faults. To read more, clic... » read more

Inevitable Bugs
By Brian Bailey - 29 Apr, 2020 - Comments: 3

Are bug escapes inevitable? That was the fundamental question that Oski Technology recently put to a group of industry experts. The participants are primarily simulation experts who, in many cases, help direct the verification directions for some of the largest systems companies. In order to promote free discussion, all comments have been anonymized, distilling the primary thoughts of the parti... » read more

Do You Trust Your IP Supplier?
By Brian Bailey - 26 Mar, 2020 - Comments: 0

How much do you trust your IP supplier, regardless of whether IP was developed in-house or by a third-party provider? And what implications does it have a system integrator? These are important questions that many companies are beginning to ask. Today, there are few methods, other than documentation, that provide the necessary information. The software industry may be ahead of the hardware i... » read more

Speeding Up Verification Using SystemC
By Ed Sperling - 23 Mar, 2020 - Comments: 0

Brett Cline, senior vice president at OneSpin Solutions, explains how adding formal verification into the high-level synthesis flow can reduce the time spent in optimization and debug by about two-thirds, why this needs to be done well ahead of RTL, starting with issues such as initialization, memory out of bounds and other issues that are difficult to find in simulation. » read more

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