tag: formal verification

Unlock Your Vision… And A Bit Of EDA History
By McKenzie Ross - 29 Mar, 2021 - Comments: 0

Repetitive patterns and hardware designs have something in common: there may be more than meets the eye. Even simple designs can have corner cases that are hard to detect by code review alone, and the situation is even more complex if third-party or legacy IP is involved. What if the IP has a deliberately hidden function? This is where verification tools like OneSpin 360 come in, to remove huma... » read more

Verification Knowledge At Your Fingertips
By Rob van Blommestein - 25 Feb, 2021 - Comments: 0

If you’re like most engineers, you’re curious about how other engineers tackle some of the most difficult challenges. What can you absorb from them and apply to your own projects? Learning from experience has tremendous value but learning from others’ experiences is arguably more valuable since the cost to acquire that knowledge is significantly cheaper. At OneSpin, we’ve lowered... » read more

AI And ML Applications Require Advanced Datapath Verification
By Kiran Vittal - 28 Jan, 2021 - Comments: 0

In popular usage, the term “artificial intelligence” (AI) once conjured up images of robot armies subjugating humans or evil computers outsmarting their users, as in '2001: A Space Odyssey.' In recent years, AI has become a part of daily life for much of the planet’s population. People use voice commands to interact with their smartphones, smart speakers and even TV remote controls. Sophi... » read more

RISC-V Becoming Less Risky With The Right Verification
By Rob van Blommestein - 25 Jan, 2021 - Comments: 1

RISC-V continues to make headlines across the electronic design industry. You may have seen the recent news that the OpenHW Group is delivering their first RISC-V core, the CV32E40P. If you attended last month’s RISC-V Summit, perhaps you attended “CORE-V: Industrial Grade Open-Source RISC-V Cores” by Rick O’Connor, president of the OpenHW Group. In this session, Rick discussed how the ... » read more

Verification’s Inflection Point
By Brian Bailey - 14 Jan, 2021 - Comments: 0

Functional verification is nearing an inflection point, brought on by rising complexity and the many tentacles that are intermixing it with other disciplines. New abstractions or different ways to approach the problems are needed. Being a verification engineer is no longer enough, except for those whose concerns is block-level verification. Most of the time and effort spent in verification i... » read more

Using Formal To Verify Safety-Critical Hardware For ISO 26262
By OneSpin Solutions - 02 Dec, 2020 - Comments: 0

Automotive technology has come a long way since the days of the Ford Model T. Today's smart vehicles not only assist their drivers with tasks such as parking, lane management, and braking, but also function as a home away from home, with WiFi hotspots and sophisticated entertainment systems. These sophisticated features are made possible by increasingly complex electronic systems—systems that... » read more

Verification Of Multi-Cycle Paths And False Paths
By Joe Mallett - 24 Sep, 2020 - Comments: 1

All chip designers know that they must take special care to avoid metastability problems when they have multiple, asynchronous clock domains. In contrast, a design in which all clocks are synchronous may appear simple. Logic synthesis ensures that the shortest paths between registers don’t have races and that the longest paths fit within the target cycle time. However, single-clock design is ... » read more

New Uses For Assertions
By Ann Mutschler - 24 Sep, 2020 - Comments: 0

Assertions have been a staple in formal verification for years. Now they are being examined to see what else they can be used for, and the list is growing. Traditionally, design and verification engineers have used assertions in specific ways. First, there are assertions for formal verification, which are used by designers to show when something is wrong. Those assertions help to pinpoint wh... » read more

Formal Solutions For SystemC/C++ Verification
By OneSpin Solutions - 23 Sep, 2020 - Comments: 0

OneSpin Solutions provides its popular 360 DV formal verification product line, which allows for both the automated checking and full assertion-based verification of SystemC/C++ design representations. This solution extends the verification capability that may be applied to abstract designs, coded in SystemC/C++ for many different use models. This white paper describes the OneSpin solution a... » read more

Is DVFS Worth The Effort?
By Brian Bailey - 10 Sep, 2020 - Comments: 2

Almost all designs have become power-aware and are being forced to consider every power saving technique, but not all of them are yielding the expected results. Moreover, they can add significant complexity into designs, increasing the time it takes to get to tapeout and boosting up the cost. Dynamic voltage and frequency scaling (DVFS) is one such power and energy saving technique now being... » read more

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