High-Level Design And High-Level Verification

By Dominik Strasser - 26 Sep, 2019 - Comments: 0

Not so long ago, some EDA vendors were painting a very attractive picture of chip design in the then-near future. The idea was that an architectural team would write a single description of the complete system in some high-level language, usually C/C++/SystemC, and that a new class of EDA tool would automatically partition the design into hardware and software, choosing the functionality of eac... » read more

Clock Domain Crossing Signoff Through Static-Formal-Simulation

By Sudeep Mondal - 22 Aug, 2019 - Comments: 0

By Sudeep Mondal and Sean O'Donohue Clocking issues are one of the most common reasons for costly design re-spins. This has been the driving factor in the ever-increasing demand for Clock Domain Crossing (CDC) analysis tools. Today, the majority of IP and SoC teams are focusing on “Structural CDC” analysis, which is important but not sufficient. Structural CDC analysis ensures that the d... » read more

A Holistic View Of RISC-V Verification

By Nicolae Tusinschi - 07 Aug, 2019 - Comments: 0

Last month, we discussed the growth of the RISC-V open processor ecosystem, the two main organizations driving it, and the role that OneSpin plays. In addition, we have become very active in the RISC-V community and have more than a dozen technical articles published, conference talks presented, and upcoming talks accepted. We tend to focus on the challenges of verifying RISC-V IP cores and sys... » read more

How To Optimize Verification

By Brian Bailey - 25 Jul, 2019 - Comments: 0

The rate of improvement in verification tools and methodologies has been nothing short of staggering, but that has created new kinds of problems for verification teams. Over the past 20 years, verification has transformed from a single language (Verilog) and tool (simulator) to utilizing many languages (testbench languages, assertion languages, coverage languages, constraint languages), many... » read more

Week In Review: Design, Low Power

By Jesse Allen - 28 Jun, 2019 - Comments: 0

VESA published the DisplayPort 2.0 standard, which allows for a max payload of 77.37 Gbps, a 3X increase in data bandwidth performance compared to DisplayPort 1.4a. The latest release also includes capabilities to address beyond 8K resolutions, higher refresh rates and HDR support at higher resolutions, multiple display configurations, and support for 4K-and-beyond VR resolutions. It is backwar... » read more

Artificial Intelligence: Let Us Get The Math Right First!

By Ravindra Aneja - 06 Jun, 2019 - Comments: 0

Artificial intelligence is a hot topic these days and therefore doesn’t require a repeat of the current and future potential uses for AI. For most people, it means technology advancements on the software side. But if you ask people who are very close to this technology domain, building your own optimized hardware chips is where a significant part of the competitive edge lies. A few days ba... » read more

Intellectual Property: Trust… But Verify

By John Hallman - 30 May, 2019 - Comments: 0

For those around the microelectronic component industry for many years, we have seen quite a transformation of capability, sourcing of the supply chain, and now threats to these devices that drive the technology in our world today. These integrated circuits (ICs), once so simple as a few transistors, have continued to follow Moore’s Law and are now made up of tens of billions of transistor... » read more

Week In Review: Design, Low Power

By Jesse Allen - 10 May, 2019 - Comments: 0

Tools & IP Cadence uncorked the latest version of JasperGold formal verification platform, providing improvements to the proof-solver algorithm and orchestration by using machine learning to select and parameterize solvers to enable faster first-time proofs and optimize successive runs for regression testing. Additionally, it increases design compilation capacity by over 2x with 50% reduct... » read more

Hardware Trojans And The Problem Of Trust In Integrated Circuits

By Sergio Marchese - 25 Apr, 2019 - Comments: 0

Electronic systems are at the core of an ever-increasing number of products and services. From power plants to automobiles, from medical devices to airplanes, from smartphones to home appliances, complex electronic systems enable an unprecedented level of automation, performance, safety, and security. Integrated circuits (ICs) are the backbone of these systems. It is of paramount importance tha... » read more

The Weather Report: 2018 Study On IC/ASIC Verification Trends

By Harry Foster - 11 Apr, 2019 - Comments: 0

Nobel Laureate Bob Dylan observed, “You don’t need a weatherman to know which way the wind blows.” Similarly, we can get a feeling for where our industry is going by attending to the flow of thought at conferences, on line, or in our daily business. But that gives us only a small window to observe the hurricane-like forces of the very large and complicated, extremely dynamic global semico... » read more

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tag: formal

High-Level Design And High-Level Verification

Clock Domain Crossing Signoff Through Static-Formal-Simulation

A Holistic View Of RISC-V Verification

How To Optimize Verification

Week In Review: Design, Low Power

Artificial Intelligence: Let Us Get The Math Right First!

Intellectual Property: Trust… But Verify

Week In Review: Design, Low Power

Hardware Trojans And The Problem Of Trust In Integrated Circuits

The Weather Report: 2018 Study On IC/ASIC Verification Trends

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